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公开(公告)号：US09735075B2
公开(公告)日：2017-08-15
申请号：US14516010
申请日：2014-10-16
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chang-Lun Lu , Shih-Ching Chen
CPC classification number: H01L23/16 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L23/562 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2924/18162
Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.
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公开(公告)号：US20170148761A1
公开(公告)日：2017-05-25
申请号：US15400608
申请日：2017-01-06
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Guang-Hwa Ma , Shih-Kuang Chiu , Shih-Ching Chen , Chun-Chi Ke , Chang-Lun Lu , Chun-Hung Lu , Hsien-Wen Chen , Chun-Tang Lin , Yi-Che Lai , Chi-Hsin Chiu , Wen-Tsung Tseng , Tsung-Te Yuan , Lu-Yi Chen , Mao-Hua Yeh
IPC: H01L23/00 , H01L21/683 , H01L23/538 , H01L21/56
CPC classification number: H01L24/96 , H01L21/568 , H01L21/6835 , H01L23/3135 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L2221/68359 , H01L2221/68372 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/82005 , H01L2224/82007 , H01L2924/12042 , H01L2924/18162 , H01L2924/351 , H01L2924/3511 , H01L2924/00
Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.
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公开(公告)号：US20170047262A1
公开(公告)日：2017-02-16
申请号：US14982276
申请日：2015-12-29
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Guang-Hwa Ma , Shih-Ching Chen , Chang-Lun Lu
IPC: H01L23/31 , H01L25/065 , H01L25/00 , H01L21/48 , H01L21/56 , H01L25/16 , H01L23/498
CPC classification number: H01L23/3128 , H01L21/4853 , H01L21/56 , H01L21/568 , H01L23/3135 , H01L23/49838 , H01L25/0652 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48464 , H01L2224/73204 , H01L2224/73265 , H01L2224/81005 , H01L2224/85005 , H01L2224/92125 , H01L2224/92247 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/37001 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/32245 , H01L2224/48247 , H01L2224/45099
Abstract: An electronic package is provided, which includes: a first circuit structure; at least first electronic element disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; a first encapsulant encapsulating the first electronic element and the first conductive element; and a second circuit structure formed on the first encapsulant and electrically connected to the first conductive element. By directly disposing the electronic element having high I/O functionality on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package. The invention further provides a method for fabricating the electronic package.
Abstract translation: 提供电子封装，其包括：第一电路结构; 至少第一电子元件设置在第一电路结构的表面上; 至少形成在所述第一电路结构的表面上的第一导电元件; 封装所述第一电子元件和所述第一导电元件的第一密封剂; 以及形成在第一密封剂上并电连接到第一导电元件的第二电路结构。 通过在电路结构上直接布置具有高I / O功能的电子元件，本发明消除了对具有芯层的封装基板的需要，从而减小了电子封装的厚度。 本发明还提供一种制造电子封装的方法。
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公开(公告)号：US20160233194A1
公开(公告)日：2016-08-11
申请号：US14986149
申请日：2015-12-31
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chang-Lun Lu , Shih-Ching Chen , Guang-Hwa Ma , Cheng-Hsu Hsiao
IPC: H01L25/065 , H01L25/00
CPC classification number: H01L25/105 , H01L21/6835 , H01L23/3128 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L25/03 , H01L2221/68345 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/83005 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2924/1533 , H01L2924/18161 , H01L2924/19103
Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.
Abstract translation: 提供一种封装结构，其包括：具有相反的第一和第二表面的电介质层; 形成在电介质层中的电路子层; 设置在电介质层的第一表面上并电连接到电路子层的电子元件; 形成在电介质层的第一表面上并电连接到电路子层的多个导电柱; 以及形成在电介质层的第一表面上并封装电子元件和导电柱的密封剂。 导电柱的上表面从密封剂露出，以允许另一个电子元件设置在导电柱上，并通过导电柱与电路子层电连接，从而克服了另一个电子元件只能 设置在封装结构的下侧，并改善封装结构的功能。
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公开(公告)号：US20150035163A1
公开(公告)日：2015-02-05
申请号：US14012402
申请日：2013-08-28
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Guang-Hwa Ma , Shih-Kuang Chiu , Shih-Ching Chen , Chun-Chi Ke , Chang-Lun Lu , Chun-Hung Lu , Hsien-Wen Chen , Chun-Tang Lin , Yi-Che Lai , Chi-Hsin Chiu , Wen-Tsung Tseng , Tsung-Te Yuan , Lu-Yi Chen , Mao-Hua Yeh
IPC: H01L23/538 , H01L23/00
CPC classification number: H01L24/96 , H01L21/568 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L2221/68372 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/82005 , H01L2224/82007 , H01L2924/12042 , H01L2924/18162 , H01L2924/351 , H01L2924/3511 , H01L2924/00
Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced.
Abstract translation: 本发明提供一种半导体封装及其制造方法，包括：将半导体元件放置在载体的凹槽中; 在所述半导体元件上形成介电层; 在所述电介质层上形成电连接到所述半导体元件的电路层; 以及在所述凹槽下方移除所述载体的第一部分以将所述载体的第二载体保持在所述凹槽的侧壁上，以使所述第二部分用作支撑部分。 本发明不需要形成硅插入件，因此最终产品的总成本大大降低。
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Patent Agency Ranking
公开(公告)号：US10796970B2
公开(公告)日：2020-10-06
申请号：US16166811
申请日：2018-10-22
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chang-Lun Lu
Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.
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公开(公告)号：US10242972B2
公开(公告)日：2019-03-26
申请号：US14986149
申请日：2015-12-31
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chang-Lun Lu , Shih-Ching Chen , Guang-Hwa Ma , Cheng-Hsu Hsiao
IPC: H01L23/58 , H01L21/78 , H01L25/10 , H01L21/683 , H01L23/538 , H01L23/31 , H01L25/03
Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.
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公开(公告)号：US10201086B2
公开(公告)日：2019-02-05
申请号：US15295010
申请日：2016-10-17
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Cheng-Hsiang Liu , Chang-Lun Lu , Jun-Cheng Liao , Cheng-Yi Chen
Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.
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公开(公告)号：US20180047610A1
公开(公告)日：2018-02-15
申请号：US15729842
申请日：2017-10-11
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Chang-Lun Lu
IPC: H01L21/683 , H01L21/66 , H01L23/373 , H01L21/48 , H01L23/498 , H01L21/56 , H01L25/16 , H01L25/065 , H01L23/00
CPC classification number: H01L21/6835 , H01L21/4846 , H01L21/4857 , H01L21/568 , H01L22/14 , H01L23/147 , H01L23/373 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5383 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L24/85 , H01L25/0655 , H01L25/16 , H01L2221/68345 , H01L2221/68381 , H01L2224/131 , H01L2224/16227 , H01L2224/48227 , H01L2224/81005 , H01L2224/85005 , H01L2924/00014 , H01L2924/153 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/014 , H01L2224/45099
Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.
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公开(公告)号：US20180042112A1
公开(公告)日：2018-02-08
申请号：US15295010
申请日：2016-10-17
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lu-Yi Chen , Cheng-Hsiang Liu , Chang-Lun Lu , Jun-Cheng Liao , Cheng-Yi Chen
CPC classification number: H05K1/181 , H05K1/111 , H05K3/341 , H05K3/3442 , H05K2201/09663 , H05K2201/10636 , Y02P70/611 , Y02P70/613
Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.
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