中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.023 seconds)

    CAPPING STRUCTURE TO REDUCE DARK CURRENT IN IMAGE SENSORS
    21.
    发明申请
    CAPPING STRUCTURE TO REDUCE DARK CURRENT IN IMAGE SENSORS 审中-公开

    公开(公告)号：US20200035741A1

    公开(公告)日：2020-01-30

    申请号：US16047455

    申请日：2018-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Eugene Chen

    IPC: H01L27/146

    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.

    High Electron Mobility Transistors
    22.
    发明申请
    High Electron Mobility Transistors 审中-公开

    公开(公告)号：US20190013399A1

    公开(公告)日：2019-01-10

    申请号：US16132793

    申请日：2018-09-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/43 ,  H01L29/201

    Abstract: The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.

    SEED LAYER STRUCTURE FOR GROWTH OF III-V MATERIALS ON SILICON
    24.
    发明申请
    SEED LAYER STRUCTURE FOR GROWTH OF III-V MATERIALS ON SILICON 有权
    用于在硅上生长III-V材料的种子层结构

    公开(公告)号：US20160322225A1

    公开(公告)日：2016-11-03

    申请号：US14699046

    申请日：2015-04-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Po-Chun Liu

    IPC: H01L21/02 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

    CPC classification number: H01L21/02694 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02617 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

    Abstract: The present disclosure relates to a structure and method of forming a GaN film on a Si substrate that includes an additional or second high temperature (HT) AlN seed layer, introduced for reducing the tensile stress of GaN on a Si substrate. The second HT AlN seed layer is disposed over a first HT AlN seed layer, and has a low V/III ratio compared to the first HT AlN seed layer. The second HT AlN seed layer has better lattice matching between Si and GaN and this reduces the tensile stress on GaN. The additional HT AlN seed layer further acts as a capping layer and helps annihilate or terminate threading dislocations (TDs) originating from a LT AlN seed layer. The second HT AlN seed layer also helps prevent Si diffusion from the substrate to the GaN film.

    Abstract translation: 本公开内容涉及在Si衬底上形成GaN膜的结构和方法，该衬底包括用于降低Si衬底上GaN的拉伸应力的额外的或第二高温（HT）AlN晶种层。 第二HT AlN种子层设置在第一HT AlN籽晶层上，并且与第一HT AlN种子层相比具有低的V / III比。 第二个HT AlN种子层在Si和GaN之间具有更好的晶格匹配，并且这降低了GaN上的拉伸应力。 附加的HT AlN种子层还起到盖层的作用，并有助于消除或终止来自LT AlN种子层的穿透位错（TD）。 第二HT AlN种子层还有助于防止Si从衬底扩散到GaN膜。

    Source/Drains In Semiconductor Devices and Methods of Forming Thereof
    25.
    发明公开
    Source/Drains In Semiconductor Devices and Methods of Forming Thereof 审中-公开

    公开(公告)号：US20230378297A1

    公开(公告)日：2023-11-23

    申请号：US18366956

    申请日：2023-08-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

    IPC: H01L29/423 ,  H01L29/78 ,  H01L29/788

    CPC classification number: H01L29/42384 ,  H01L29/785 ,  H01L29/7889

    Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

    High electron mobility transistors
    27.
    发明授权
    High electron mobility transistors 有权

    公开(公告)号：US10991819B2

    公开(公告)日：2021-04-27

    申请号：US16132793

    申请日：2018-09-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/43

    Abstract: The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.

    LOADING EFFECT REDUCTION THROUGH MULTIPLE COAT-ETCH PROCESSES
    29.
    发明申请
    LOADING EFFECT REDUCTION THROUGH MULTIPLE COAT-ETCH PROCESSES 审中-公开

    公开(公告)号：US20190252193A1

    公开(公告)日：2019-08-15

    申请号：US16396429

    申请日：2019-04-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

    IPC: H01L21/283 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/308

    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

    Loading effect reduction through multiple coat-etch processes
    30.
    发明授权
    Loading effect reduction through multiple coat-etch processes 有权

    公开(公告)号：US10276392B2

    公开(公告)日：2019-04-30

    申请号：US15642559

    申请日：2017-07-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

    IPC: H01L21/306 ,  H01L21/283 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

Patent Agency Ranking