公开(公告)号：US20020179329A1

公开(公告)日：2002-12-05

申请号：US10160179

申请日：2002-06-04

申请人： DAI NIPPON PRINTING CO., LTD.

发明人： Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

IPC分类号： H05K001/16 ,  H01F007/06 ,  H05K003/36

CPC分类号： H05K1/162 ,  H05K1/095 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0338 ,  H05K2203/1189 ,  Y10T29/4902 ,  Y10T29/49099 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

摘要： A fabricating method of a wiring board provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste and dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has a first surface and a second surface; arranging an insulating board having thermo-plasticity and thermo-setting properties so as to face the first surface of the first metal foil, and arranging the first surface side of the second metal foil so as to face a surface different from a surface to which the first metal foil faces of the insulating board; forming a double-sided wiring board by stacking, pressurizing and heating the arranged first metal foil, insulating board, and second metal foil, and thereby integrating these; and patterning the first metal foil and/or the second metal foil.

摘要翻译： 公开了一种具有无源元件的布线板的制造方法。 制造方法包括在第一金属箔和第二金属箔的至少一个第一表面上涂覆电阻浆料和电介质浆料中的一种或两种，每个第一表面具有第一表面和第二表面; 布置具有热塑性和热固性的绝缘板，以便面对第一金属箔的第一表面，并且将第二金属箔的第一表面侧布置成面对不同于表面的表面 绝缘板的第一金属箔面; 通过对所配置的第一金属箔，绝缘板和第二金属箔进行堆叠，加压和加热来形成双面布线板，从而将它们集成; 以及图案化第一金属箔和/或第二金属箔。

公开(公告)号：US20020148641A1

公开(公告)日：2002-10-17

申请号：US10110678

申请日：2002-04-16

发明人： Fumihiro Minami ,  Yukari Yamasaki ,  Mutsuo Sekiya

IPC分类号： H05K001/16 ,  H01R012/04 ,  H05K003/34

CPC分类号： H01R33/9456 ,  H01R33/7635 ,  H01R33/7685 ,  H01R33/9756 ,  H01R2201/08 ,  H01R2201/26 ,  H05K3/301 ,  Y10T29/49144

摘要： A mounting board has a board, retaining members mounted on the upper surface of the board, and a part retained by the retaining members. The part is mounted such that at least a part thereof is arranged below the lower surface of the board, and that the part is electrically connected to the board through the retaining members. Such an arrangement as described above eliminates the need of connecting the discharge gap element to the board by using lead wires, and of mounting it on the upper surface of the board. This lowers the height of the board and admits an elevated part.

摘要翻译： 安装板具有板，安装在板的上表面上的保持构件和由保持构件保持的部分。 该部件被安装成使得其至少一部分布置在板的下表面下方，并且该部件通过保持构件与板电连接。 如上所述的这种布置消除了通过使用引线将放电间隙元件连接到电路板并将其安装在电路板的上表面上的需要。 这降低了板的高度，并承认升高的部分。

公开(公告)号：US20020134581A1

公开(公告)日：2002-09-26

申请号：US10155628

申请日：2002-05-24

申请人： Intel Corporation

发明人： David G. Figueroa ,  Yuan-Liang Li ,  Huong T. Do

IPC分类号： H05K001/16 ,  H01G004/38 ,  H01L029/00

CPC分类号： H01L23/642 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/19105 ,  H05K1/141 ,  H05K1/162 ,  Y10T29/435 ,  H01L2924/00

摘要： A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provides a ground plane, while the other conductive layer provides a power plane.

摘要翻译： 与集成电路封装相关联的混合电容为裸片负载提供多级多余的片外电容。 混合电容器包括嵌入在封装内的低电感并联板电容器，并且电连接到片外电容的第二源极。 平行板电容器设置在管芯下方，并且包括顶部导电层，底部导电层和电绝缘顶层和底层的薄介电层。 片外电容的第二个源是一组自对准通孔电容器和/或一个或多个分立电容器和/或附加的平行板电容器。 每个自对准通孔电容器嵌入在封装内，并具有内部导体和外部导体。 内部导体电连接到顶部或底部导电层，并且外部导体电连接到另一个导电层。 分立电容器电连接到从导电层到封装表面的触点。 在操作期间，低电感平行板电容器的导电层之一提供接地平面，而另一导电层提供电源平面。

公开(公告)号：US20020092674A1

公开(公告)日：2002-07-18

申请号：US10096714

申请日：2002-03-12

发明人： Yoshihiro Yoneda

IPC分类号： H05K001/16

CPC分类号： H01L24/16 ,  H01L23/49822 ,  H01L2224/10175 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81395 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0023 ,  H05K3/184 ,  H05K3/4661 ,  H05K2201/09563 ,  H05K2201/09781 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A surface-mounting substrate, for mounting thereon a part such as a semiconductor device, which comprises a core substrate, a plurality of layers of patterned wiring lines, which are separated from each other by an insulation layer interposed therebetween, vias piercing through the insulation layer to connect the wiring lines at the adjacent layers to each other, and a layer of connecting terminals to mount a part on the surface-mounting substrate, each of the connecting terminals connecting with the wiring line at the outermost layer of wiring lines, wherein the connecting terminal is filled in an outermost insulation layer provided at the surface of the surface-mounting substrate, and has a surface exposed at substantially the same level as the level of the surface of the outermost insulation layer. A structure comprising a surface-mounting substrate and a part mounted thereon, which comprises, as the substrate used, the surface-mounting substrate of the invention, is also disclosed.

摘要翻译： 表面安装基板，用于在其上安装诸如半导体器件的部件，其包括芯基板，多层图案化布线，它们之间通过绝缘层彼此分离，通孔穿过绝缘体 层，将相邻层的布线彼此连接，以及一层连接端子，以在表面安装基板上安装部件，每个连接端子与布线的最外层的布线连接，其中 连接端子填充在设置在表面安装基板的表面的最外层绝缘层，并且具有以与最外层绝缘层的表面水平基本相同的水平露出的表面。 还公开了一种包括表面安装基板和安装在其上的部件的结构，其包括作为所使用的基板的本发明的表面安装基板。

公开(公告)号：US20020085360A1

公开(公告)日：2002-07-04

申请号：US09752660

申请日：2000-12-28

发明人： Yutaka Doi

IPC分类号： H05K001/16 ,  H05K001/03 ,  H05K001/09

CPC分类号： H05K1/16 ,  H05K1/162 ,  H05K1/167 ,  H05K3/0017 ,  Y10T29/4913 ,  Y10T29/49155

摘要： Compositions and methods are provided whereby electronic components may be produced that comprise a) a substrate layer; b) an insulator layer coupled to the substrate layer, wherein the insulator layer comprises at least two different kinds of embedded passive components; and c) at least one additional layer coupled to the insulator layer. A preferred method comprises a) imaging an insulator layer to create a first pattern on the insulator layer; b) etching the first pattern on the insulator layer to create a first compartment in the insulator layer; c) filling the first compartment with a first material to form a first passive component; d) imaging the insulator layer to create a second pattern on the insulator layer; e) etching the second pattern on the insulator layer to create a second compartment in the insulator layer; and f) filling the second compartment with a second material to form a second passive component.

摘要翻译： 提供了组合物和方法，其中可以生产包括a）基底层的电子部件; b）耦合到所述衬底层的绝缘体层，其中所述绝缘体层包括至少两种不同种类的嵌入式无源组件; 和c）至少一个连接到所述绝缘体层的附加层。 优选的方法包括：a）对绝缘体层进行成像以在绝缘体层上产生第一图案; b）蚀刻绝缘体层上的第一图案以在绝缘体层中形成第一隔室; c）用第一材料填充第一隔室以形成第一无源部件; d）对所述绝缘体层进行成像以在所述绝缘体层上产生第二图案; e）蚀刻绝缘体层上的第二图案以在绝缘体层中形成第二隔间; 以及f）用第二材料填充所述第二隔室以形成第二无源部件。

公开(公告)号：US20020066592A1

公开(公告)日：2002-06-06

申请号：US09727477

申请日：2000-12-04

发明人： Wen Feng Cheng

IPC分类号： H05K001/16

CPC分类号： H01L24/73 ,  H01L23/3675 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3025 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention proposes a BGA package capable of increasing heat-spreading effect and preventing EMI. The BGA package of the present invention comprises a BGA substrate with a conductive ring formed on the periphery thereof. The BGA substrate has a metal layer electrically connected to the conductive ring. At least an IC chip is arranged on the BGA substrate. A cap capable of conducting both electricity and heat covers over the chip. The periphery of the cap is sealed with the conductive ring. Raise parts formed in the cap contacts with the chip to conduct heat out. Moreover, the cap, the conductive ring, and the metal layer can form a shield of EMI for the chip.

摘要翻译： 本发明提出一种能够增加散热效果并防止EMI的BGA封装。 本发明的BGA封装包括在其周边形成有导电环的BGA衬底。 BGA衬底具有与导电环电连接的金属层。 至少一个IC芯片布置在BGA基板上。 能够在芯片上覆盖电和热盖的盖子。 盖的周边用导电环密封。 将形成在帽中的部件升起与芯片接触以传导热量。 此外，盖，导电环和金属层可以形成用于芯片的EMI屏蔽。

公开(公告)号：US20020050406A1

公开(公告)日：2002-05-02

申请号：US09983502

申请日：2001-10-24

发明人： Takeshi Yamashita

IPC分类号： H05K001/16

CPC分类号： H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

摘要： Test terminals connected to output lead sections are divided into blocks, and in each of the blocks, an outermost pair of the test terminals extends inwards from the output lead sections to oppose each other, and the pair is located relatively far from a place where a liquid crystal driver LSI chip is mounted.

公开(公告)号：US20020042988A1

公开(公告)日：2002-04-18

申请号：US09836298

申请日：2001-04-18

发明人： Ulf Jansson

IPC分类号： H05K001/03 ,  H05K001/16

CPC分类号： H05K3/303 ,  H05K3/341 ,  H05K7/142 ,  H05K2201/10409 ,  H05K2201/10598 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/53174

摘要： The invention relates to a method for mounting at least one electronic or mechanical component on a printed board comprising the steps of: surface-mounting at least one guide element on the printed board or placing the at least one guide element in a dead end hole in the printed board, fastening the at least one guide element to the printed board by soldering before guiding the at least one electronic or mechanical component towards the printed board, and placing the at least one electronic or mechanical component on the printed board with the help of the at least one guide element. The invention also relates to a guide element and a electronic or mechanical component to be used in the method.

摘要翻译： 本发明涉及一种用于将至少一个电子或机械部件安装在印刷电路板上的方法，包括以下步骤：将至少一个引导元件表面安装在印刷电路板上，或将至少一个引导元件放置在死角孔中 所述印刷电路板通过焊接将所述至少一个引导元件紧固到所述印刷电路板，然后在将所述至少一个电子或机械部件引向所述印刷电路板之前将所述至少一个电子或机械部件放置在所述印刷电路板上，借助于 所述至少一个引导元件。 本发明还涉及在该方法中使用的引导元件和电子或机械部件。

公开(公告)号：US20020005293A1

公开(公告)日：2002-01-17

申请号：US09120204

申请日：1998-07-22

发明人： TOMOO MURAKAMI

IPC分类号： H05K001/16 ,  H05K001/03 ,  H05K003/34

CPC分类号： H01L24/29 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/18301 ,  H01L2924/3025 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49169 ,  Y10T29/53174 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device comprises a plurality of bump electrodes at least to one surface. A circuit substrate is formed with a laminate structure having an inner layer circuit and a mounting pad is formed on the substrate. The mounting pad has a concave portion and the bottom of the concave portion is in contact with the inner layer circuit. Further, an sealing resin is provided on the substrate. The bump electrode and the concave portion of the mounting pad are opposed, and the bump electrode is pressed to the bottom of the concave portion of the mounting pad, thereby deforming the pointed shape portion at the top end of the bump electrode. By the deformation the pointed shape portion, the contact portion between the bump electrode and the mounting pad is gradually enlarged from a point to a plane. After deforming the bump electrode by a predetermined amount, the sealing resin is hardened and the semiconductor device is mounted on a substrate.

摘要翻译： 半导体器件在至少一个表面上包括多个凸起电极。 电路基板形成有具有内层电路的层压结构，并且在基板上形成安装焊盘。 安装垫具有凹部，凹部的底部与内层电路接触。 此外，在基板上设置密封树脂。 凸起电极和安装焊盘的凹部相对，并且凸起电极被压到安装焊盘的凹部的底部，从而使突起电极的顶端处的尖形部分变形。 通过变形尖锐的形状部分，突起电极和安装衬垫之间的接触部分从点到平面逐渐扩大。 在将凸起电极变形预定量之后，密封树脂硬化，将半导体器件安装在基板上。

公开(公告)号：US20010030060A1

公开(公告)日：2001-10-18

申请号：US09745853

申请日：2000-12-22

发明人： David W. Carroll

IPC分类号： H05K001/16

CPC分类号： H05K1/0271 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09781 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/2009 ,  H05K2201/2018 ,  H01L2924/00

摘要： A computing device unit includes a rigid-to-flexible protection mechanism for e.g. die-on-flex technologies. According to one example, a flexible electronic device includes an electronic component for generating or receiving signals, a substrate for supporting the electronic component, and structure for stiffening the substrate, the structure being disposed to provide the substrate with a first rigidity adjacent the electronic component and a second rigidity more distant from the electronic component, the first rigidity being greater than the second rigidity such that the electronic component is protected against excessive flexing.

摘要翻译： 一种计算设备单元包括一个刚性到柔性的保护机制。 模具技术。 根据一个示例，柔性电子设备包括用于产生或接收信号的电子部件，用于支撑电子部件的基板和用于加强基板的结构，该结构被设置成为基板提供邻近电子部件的第一刚性 以及比电子部件更远的第二刚性，第一刚性大于第二刚性，使得电子部件被保护以防过度弯曲。