公开(公告)号：US20170170175A1

公开(公告)日：2017-06-15

申请号：US14968917

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts with sidewalls of the opposite spacers.

公开(公告)号：US09673331B2

公开(公告)日：2017-06-06

申请号：US14930231

申请日：2015-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.

公开(公告)号：US20170141189A1

公开(公告)日：2017-05-18

申请号：US14941664

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L29/1083 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET includes a substrate, a plurality of insulators disposed on the substrate, a gate stack and a strained material. The substrate includes at least one semiconductor fin and the semiconductor fin includes at least one modulation portion distributed therein. The semiconductor fin is sandwiched by the insulators. The gate stack is disposed over portions of the semiconductor fin and over portions of the insulators. The strained material covers portions of the semiconductor fin that are revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.

公开(公告)号：US09614089B2

公开(公告)日：2017-04-04

申请号：US14827092

申请日：2015-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L21/28247 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a protection element over the gate stack. A top of the protection element is wider than a bottom of the protection element. The semiconductor device structure also includes a spacer element over a side surface of the protection element and a sidewall of the gate stack. The semiconductor device structure further includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

公开(公告)号：US09559100B2

公开(公告)日：2017-01-31

申请号：US15086433

申请日：2016-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/31055 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device includes first and second Fin FET transistors and a separation plug made of an insulating material and disposed between the first and second Fin FET transistors. The first Fin FET transistor includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET transistor includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In across section along the second direction and across the first gate electrode, the second gate electrode and the separation plug, the separation plug has a tapered shape having atop size smaller than a bottom size.

Abstract translation: 半导体器件包括第一和第二Fin FET晶体管和由绝缘材料制成并分布在第一和第二Fin FET晶体管之间的分离插头。 第一Fin FET晶体管包括在第一方向上延伸的第一鳍结构，形成在第一鳍结构上的第一栅极电介质和形成在第一栅极电介质上并且垂直于第一方向延伸的第二方向的第一栅电极。 第二鳍FET晶体管包括第二鳍结构，形成在第二鳍结构上的第二栅极电介质和形成在第一栅极电介质上并延伸第二方向的第二栅电极。 在沿着第二方向跨过第一栅电极，第二栅电极和分离塞的横截面中，分离塞具有顶部尺寸小于底部尺寸的锥形形状。

公开(公告)号：US20250169101A1

公开(公告)日：2025-05-22

申请号：US19027821

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H10D30/62 ,  G01N21/88 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/67 ,  H10D30/01 ,  H10D64/27 ,  H10D64/66 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

公开(公告)号：US12176424B2

公开(公告)日：2024-12-24

申请号：US17671230

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

公开(公告)号：US12166096B2

公开(公告)日：2024-12-10

申请号：US18301554

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Yu-Fan Peng ,  Li-Ting Chen ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Wei-Chung Sun ,  Yuan-Ching Peng ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Pei-Yi Liu ,  Jing Yi Yan

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US20240379826A1

公开(公告)日：2024-11-14

申请号：US18782065

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

公开(公告)号：US11942363B2

公开(公告)日：2024-03-26

申请号：US17818608

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/76 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/30608 ,  H01L21/30655 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/3065

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.