公开(公告)号：US09621031B1

公开(公告)日：2017-04-11

申请号：US14923776

申请日：2015-10-27

Applicant: STMicroelectronics International N.V.

Inventor： Jitendra Jain ,  Ranajay Mallik

IPC: H05B37/04 ,  H02M3/04 ,  H05B33/08

CPC classification number: H02M3/04 ,  H05B33/0815 ,  H05B33/0827 ,  H05B33/0845 ,  H05B33/0887 ,  Y02B20/347

Abstract: A tunable voltage regulator has an output generating a variable voltage and an input that receives a trimming signal for controlling the output variable voltage. A current regulating circuit operates to regulate a current flowing through a load in response to the variable voltage. A control circuit senses the variable voltage and a drop voltage of the current regulating circuit, and determines whether the current regulating circuit has failed to regulate the current flowing through the load because the variable voltage is too low. In response thereto, the control circuit generates the trimming signal to set the variable voltage to a value sufficient for the current regulating circuit to successfully regulate the current flowing through the load.

公开(公告)号：US20170064321A1

公开(公告)日：2017-03-02

申请号：US14837051

申请日：2015-08-27

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vindhyeshwari Kumar KASHYAP ,  Ajit Singh MOTRA ,  Mahesh Narain SHUKLA ,  Tarun SINGAL

IPC: H04N19/44 ,  H04N19/85 ,  H04N19/423 ,  H04N19/436

CPC classification number: H04N19/436 ,  H04N19/91

Abstract: A video decoder includes an input configured to receive a plurality of bins of a video digital data stream to be decoded. A processor and a memory associated therewith are configured to perform parallel decoding of multiple bins of the plurality of bins in a given processing cycle based upon a table containing delta range values and probable symbols.

Abstract translation: 视频解码器包括被配置为接收待解码的视频数字数据流的多个存储槽的输入。 处理器和与其相关联的存储器被配置为基于包含增量范围值和可能符号的表，在给定处理周期内执行多个箱中的多个箱的并行解码。

公开(公告)号：US09559665B2

公开(公告)日：2017-01-31

申请号：US14788714

申请日：2015-06-30

Applicant: STMicroelectronics International N.V.

Inventor： Amit Chhabra

IPC: H03K3/011 ,  G11C11/417 ,  H03K17/687 ,  H01L27/11

CPC classification number: H03K3/011 ,  G01K3/005 ,  G01K7/01 ,  G11C5/146 ,  G11C7/04 ,  G11C11/417 ,  H01L27/1104 ,  H03K17/687

Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A threshold detector selectively applies either a first voltage or second voltage to the doped well region based on whether the temperature of the semiconductor substrate is above or below a threshold temperature.

Abstract translation: 集成电路管芯包括形成在半导体衬底中的多个晶体管，在半导体衬底的掺杂阱区域上的晶体管的体区。 阈值检测器基于半导体衬底的温度是高于还是低于阈值温度来选择性地将第一电压或第二电压施加到掺杂阱区。

公开(公告)号：US20170005780A1

公开(公告)日：2017-01-05

申请号：US14788721

申请日：2015-06-30

Applicant: STMicroelectronics International N.V.

Inventor： Tapas Nandy ,  Nitin Gupta

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  G06F1/10 ,  H04J3/0685 ,  H04L1/0026 ,  H04L5/00 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033 ,  H04L7/0337

Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

Abstract translation: 源同步数据传输系统包括数据发送装置和数据接收装置。 专用数据线将数据信号从数据传输装置传送到数据接收装置。 专用时钟线将数据传输装置的调制时钟信号传送到数据接收装置。 数据传输装置包括：时钟数据驱动器，被配置为通过调制调制时钟信号的幅度将数据编码成调制时钟信号。 因此，源同步数据传输系统的时钟线携带时钟信号和附加数据。

公开(公告)号：US20170005568A1

公开(公告)日：2017-01-05

申请号：US14788704

申请日：2015-06-30

Applicant: STMicroelectronics International N.V.

Inventor： Saurabh Sona

IPC: H02M1/32 ,  H02P7/00 ,  H02M7/06

CPC classification number: H02M1/32 ,  H02H7/1222 ,  H02M5/458 ,  H02P7/00 ,  H02P29/0241

Abstract: An overvoltage protection device protects a half bridge circuit that receives a supply voltage. The overvoltage protection device includes a high speed overvoltage detector that receives the supply voltage, detects whether an overvoltage situation is present, and outputs an overvoltage signal that disables the switches of the half bridge circuit before the switches can be damaged by the overvoltage situation. With both the switches of the half-bridge disabled, the entire supply voltage appears across the two switches in series, by which each switch only receives half the entire voltage. Thus, by quickly disabling both switches of the half-bridge each switch only needs a maximum voltage rating equal to half the maximum voltage rating of the half bridge circuit as a whole. This leads to reduced size and cost for the switches of the half-bridge circuit.

Abstract translation: 过电压保护装置保护接收电源电压的半桥电路。 过压保护装置包括接收电源电压的高速过电压检测器，检测是否存在过电压情况，并且在开关可能被过电压情况损坏之前输出禁用半桥电路的开关的过电压信号。 由于半桥的两个开关都被禁用，整个电源电压出现在串联的两个开关中，每个开关仅接收整个电压的一半。 因此，通过快速禁用半桥的两个开关，每个开关仅需要等于半桥电路整体的最大额定电压的一半的最大额定电压。 这导致半桥电路的开关的尺寸和成本降低。

公开(公告)号：US09501980B2

公开(公告)日：2016-11-22

申请号：US13708604

申请日：2012-12-07

Applicant: STMicroelectronics International N.V.

Inventor： Nishant Omar ,  Ranajay Mallik

IPC: G09G5/10 ,  G09G3/34 ,  G06F3/14 ,  G09G3/32

CPC classification number: G09G3/3413 ,  G06F3/1446 ,  G09G3/32

Abstract: A display panel comprises an array of light elements arranged in n rows by m columns. At least one driver is configured to drive one of said columns and rows, wherein the or each driver is configured to drive each of said columns or said rows. A plurality of the display panels may be used together to form a display panel system.

Abstract translation: 显示面板包括以n行×m列排列的光元件阵列。 至少一个驱动器被配置为驱动所述列和行之一，其中所述或每个驱动器被配置为驱动所述列或所述行中的每一个。 多个显示面板可以一起使用以形成显示面板系统。

公开(公告)号：US20160315621A1

公开(公告)日：2016-10-27

申请号：US14691738

申请日：2015-04-21

Applicant: STMicroelectronics International N.V.

Inventor： Jeet Narayan Tiwari ,  Nitin Gupta

IPC: H03K21/02

CPC classification number: H03K21/026 ,  H03K21/00 ,  H03K23/00 ,  H03K23/58 ,  H03K23/667 ,  H03K23/68

Abstract: A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M−1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.

Abstract translation: 本文描述了将时钟信号除以具有M个最高有效位的N位的输入信号的方法。 该方法包括使用分频器将时钟信号除以时钟信号的2N-M分频之外的输入信号2N-M-1的最高有效位。 使用分频器，将时钟信号除以时钟信号的2N-M分频之外的最高有效位和最低有效位之和。 使用分频器也可以将时钟信号除以2N-M，2N-M次。

公开(公告)号：US20160308431A1

公开(公告)日：2016-10-20

申请号：US14957752

申请日：2015-12-03

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Patrik ARNO ,  Eric CIROT

IPC: H02M1/00 ,  H05K3/32 ,  H02M3/158

CPC classification number: H05K3/32 ,  H02M1/08 ,  H02M3/1588 ,  H02M7/483 ,  H02M2001/0054 ,  H02M2007/4835 ,  H03K17/162 ,  Y02B70/1466 ,  Y02B70/1491

Abstract: A circuit is for controlling a power transistor of a DC/DC converter. The circuit may include first and second first transistors coupled in series between a first reference voltage and a control terminal of the power transistor, the first and second transistors defining a first junction node. The circuit may include third and fourth transistors coupled in series between the control terminal and a second reference voltage, the third and fourth transistors defining a second junction node. The first and second transistors may have a first conductivity type different from a second conductivity type of the third and fourth transistors. The circuit may include a capacitive element coupled between the first and second junction nodes.

Abstract translation: 电路用于控制DC / DC转换器的功率晶体管。 电路可以包括串联耦合在第一参考电压和功率晶体管的控制端之间的第一和第二晶体管，第一和第二晶体管限定第一结节点。 电路可以包括串联耦合在控制端和第二参考电压之间的第三和第四晶体管，第三和第四晶体管限定第二连接节点。 第一和第二晶体管可以具有不同于第三和第四晶体管的第二导电类型的第一导电类型。 电路可以包括耦合在第一和第二连接节点之间的电容元件。

公开(公告)号：US09466347B1

公开(公告)日：2016-10-11

申请号：US14971403

申请日：2015-12-16

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Marco Pasotti ,  Vikas Rana

IPC: G11C8/10 ,  G11C13/00

CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069

Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, a plurality of wordlines coupled to the array of PCM cells, and a row decoder circuit coupled to the plurality of wordlines. The row decoder circuit includes a first low voltage logic gate and a first high voltage level shifter coupled to the first low voltage logic gate. The row decoder circuit also includes a second low voltage logic gate, a second high voltage level shifter coupled to the second low voltage logic gate, and a first low voltage logic circuit coupled to the second low voltage logic gate. In addition, the row decoder circuit includes a second low voltage logic circuit coupled to the second low voltage logic gate, and a low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and an output coupled to a selected wordline.

Abstract translation: 集成电路包括相变存储器（PCM）单元的阵列，耦合到PCM单元阵列的多个字线以及耦合到多个字线的行解码器电路。 行解码器电路包括耦合到第一低电压逻辑门的第一低电压逻辑门和第一高电压电平移位器。 行解码器电路还包括第二低电压逻辑门，耦合到第二低电压逻辑门的第二高电压电平移位器和耦合到第二低电压逻辑门的第一低电压逻辑电路。 此外，行解码器电路包括耦合到第二低电压逻辑门的第二低电压逻辑电路和具有耦合到第一和第二低电压逻辑门的输出的输入的低电压字线驱动器，以及耦合到 到一个选定的字线。

公开(公告)号：US09438254B1

公开(公告)日：2016-09-06

申请号：US14718597

申请日：2015-05-21

Applicant: STMicroelectronics International N.V.

Inventor： Abhirup Lahiri

IPC: H03L7/06 ,  H03L7/085

CPC classification number: H03L7/0891 ,  H03L7/099

Abstract: A phase-locked-loop includes a phase-frequency-detector (PFD) comparing phases of an input signal and feedback signal, and generating therefrom control signals. An attenuation circuit in series with the PFD includes a filter between a voltage-controlled-oscillator (VCO) control node and ground. A buffer is coupled to the VCO control node. An impedance network is coupled to the VCO control node and has an impedance element coupled to a first current source so voltage at the VCO control node increases when control signals indicate the phase of the input signal leads the feedback signal, and coupled to a second current source so voltage at the VCO control node decreases when control signals indicate a lagging phase. A VCO is coupled to the VCO control node to generate an output signal, with the phase of the output signal matching the input signal. The feedback signal is based upon the output signal.

Abstract translation: 锁相环包括比较输入信号和反馈信号的相位的相位频率检测器（PFD），并从其产生控制信号。 与PFD串联的衰减电路包括压控振荡器（VCO）控制节点和地之间的滤波器。 缓冲器耦合到VCO控制节点。 阻抗网络耦合到VCO控制节点并且具有耦合到第一电流源的阻抗元件，因此当控制信号指示输入信号的相位引导反馈信号并耦合到第二电流时，VCO控制节点处的电压增加 当控制信号指示滞后相位时，VCO控制节点处的源极电压降低。 VCO耦合到VCO控制节点以产生输出信号，输出信号的相位与输入信号匹配。 反馈信号基于输出信号。