-
公开(公告)号：US09569308B1
公开(公告)日：2017-02-14
申请号：US14328941
申请日：2014-07-11
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brian S. Leibowitz
CPC classification number: G06F11/1048 , G06F11/1044 , G06F11/1076 , H03M13/356 , H03M13/6502
Abstract: A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.
Abstract translation: 存储器控制器可操作在误差检测/校正模式中，其中N个校正子值分别应用于数据量的N个数据字，但是单个奇偶校验位在数据量的所有N个数据字上被共享。
-
352.发明授权Drift adjustment in timing signal forwarded from memory controller to memory device based on a detected phase delay occurring on a second timing signal with a different frequency 有权基于在具有不同频率的第二定时信号上发生的检测到的相位延迟，从存储器控制器向存储器件转发的定时信号中的漂移调整公开(公告)号：US09568942B2
公开(公告)日：2017-02-14
申请号：US14961077
申请日：2015-12-07
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
IPC: G06F1/00 , G06F1/08 , H03L7/099 , H04L7/00 , H03L7/081 , H03L7/07 , H04L7/10 , G06F13/16 , G06F1/10
CPC classification number: G06F1/08 , G06F1/10 , G06F13/1673 , G06F13/1689 , H03L7/07 , H03L7/0814 , H03L7/0995 , H04L7/0008 , H04L7/0033 , H04L7/10 , Y02D10/14
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
Abstract translation: 一种存储器系统，其中通过测量在具有低于第一定时的频率的第二定时信号中出现的实际相位延迟来确定在存储器件中用于数据传输的第一定时信号的分配中将发生的定时漂移 并且分布在模拟第一定时信号的分布的至少一部分的漂移特性的一个或多个电路中。 实际的相位延迟在存储器件中确定并提供给存储器控制器，使得用于数据传输的定时信号的相位可以基于所确定的定时漂移来调整。
-
公开(公告)号：US09568544B2
公开(公告)日：2017-02-14
申请号：US14250191
申请日：2014-04-10
Applicant: RAMBUS INC.
Inventor： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
IPC: G01R31/02 , G01R31/28 , G01R31/317
CPC classification number: G01R31/31722 , G01R31/2851 , G01R31/31723 , H01L2224/05554 , H01L2224/48137 , H01L2224/48145 , H01L2924/00012
Abstract: A system includes a first integrated circuit configured to operate in at least a normal mode and a test mode and a second integrated circuit, where both the first integrated circuit and the second integrated circuit are disposed within a same semiconductor device package. The system further includes a first terminal, external to the semiconductor device package, electronically coupled to the first integrated circuit and the second integrated circuit. The first terminal is electronically coupled to a buffer in the second integrated circuit and used to convey signals to or from the first integrated circuit.
Abstract translation: 一种系统包括被配置为在至少正常模式和测试模式下工作的第一集成电路和第二集成电路，其中第一集成电路和第二集成电路均设置在相同的半导体器件封装内。 该系统还包括电子耦合到第一集成电路和第二集成电路的半导体器件封装外部的第一端子。 第一端子电耦合到第二集成电路中的缓冲器，并用于将信号传送到第一集成电路或从第一集成电路传送信号。
-
公开(公告)号：US09564911B2
公开(公告)日：2017-02-07
申请号：US14858830
申请日：2015-09-18
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Barry W. Daly , Dustin T. Dunwell , Anthony Chan Carusone , John C. Eble, III
CPC classification number: H03L7/24 , H03B27/00 , H03K3/0315 , H03K3/0322 , H03K5/133 , H03K5/1565
Abstract: Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.
Abstract translation: 描述了具有乘法注入锁定振荡器的方法和装置。 一些实施例包括脉冲发生器和注射器以及一个或多个注入锁定的振荡器。 脉冲发生器和注射器的输出可以注入到注入锁定振荡器的相应注入点。 在包括多个注入锁定的振荡器的实施例中，每个注入锁定振荡器的输出可以被注入到下一个注入锁定振荡器的相应注入点。 一些实施例通过动态地修改注入锁定振荡器的环路长度和/或通过使用占空比校正器和/或通过复用/混合来自注入锁定振荡器的多个延迟元件的输出来减少确定性抖动。
-
公开(公告)号：US09563597B2
公开(公告)日：2017-02-07
申请号：US14386561
申请日：2012-12-20
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern , Brian S. Leibowitz , Wayne Frederick Ellis , Akash Bansal , John Welsford Brooks , Kishore Ven Kasamsetty
CPC classification number: G11C8/18 , G06F13/161 , G06F13/1647 , G06F13/1657 , G06F13/4234 , G11C5/02 , G11C5/04 , G11C7/10 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C2207/2254
Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
Abstract translation: 在允许每个等级的时钟分配树被允许在宽范围内漂移的多存储器存储器系统（例如，低功率存储器系统）中，通过使用引起每个寻址的技术来促进等级之间的命令的精细交错 排名适当地采样旨在该等级的命令，尽管有漂移。 执行这种“微线程”的能力提供了显着增强的存储器容量，而不牺牲单级系统的性能。 本公开提供了适于这些目的的方法，存储器控制器，存储器件和系统设计。
-
Patent Agency Ranking
公开(公告)号：US09537617B2
公开(公告)日：2017-01-03
申请号：US15019483
申请日：2016-02-09
Applicant: Rambus Inc.
Inventor： Srinivasaraman Chandrasekaran , Kunal Desai
CPC classification number: H04L1/205 , G01R31/31709 , G01R31/31726 , H04L1/241 , H04L1/242 , H04L7/0079 , H04L7/0083 , H04L7/10
Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.
Abstract translation: 集成电路包括多个接收器，每个接收器具有时钟和数据恢复电路。 可以使第一接收机中的第一本地时钟恢复电路产生模拟要测试的条件的测试时钟，并且使包括第二本地时钟恢复电路在内的多个接收机中的第二接收机使用该测试 时钟代替参考时钟，同时在其输入端接收测试数据序列。 接收机中的时钟和数据恢复电路可以包括响应于环路控制信号的时钟控制环路，以响应于（i）用于正常操作或在测试期间的相应数据信号中的选择性的一个来选择性地修改所选择的参考时钟以产生本地时钟 ，以及（ii）施加到时钟控制回路的测试信号，在这种情况下产生测试时钟。
-
公开(公告)号：US09521349B2
公开(公告)日：2016-12-13
申请号：US14727869
申请日：2015-06-02
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Jay Endsley , Michael Guidash
CPC classification number: H04N5/378 , H04N5/3454 , H04N5/3698 , H04N5/376
Abstract: Pixels within an image sensor pixel array are sampled by corresponding conditional read circuitry. A zero pixel value is outputted for each pixel associated with a sample less than a conversion threshold, and a saturated pixel value is outputted for each pixel associated with a sample greater than or equal to a saturation threshold. Samples greater than or equal to the conversion threshold and less than the saturation threshold are converted by an ADC, and a converted pixel value is output for each associated above threshold pixel. The ADC (along with any corresponding amplifiers) are powered on for a variable period depending on the number of pixels needing conversion during the conversion of such samples during a read period, and are powered off for the remainder of the read period.
Abstract translation: 图像传感器像素阵列内的像素通过相应的条件读取电路进行采样。 对于与小于转换阈值的样本相关联的每个像素输出零像素值，并且对于与大于或等于饱和阈值的样本相关联的每个像素输出饱和像素值。 通过ADC转换大于或等于转换阈值且小于饱和阈值的样本，并为每个相关联的上述阈值像素输出转换的像素值。 取决于在读取周期期间这样的样本的转换期间需要转换的像素的数量，ADC（以及任何相应的放大器）以及可变周期被加电，并且在读取周期的其余部分中断电。
-
公开(公告)号：US09521337B1
公开(公告)日：2016-12-13
申请号：US13936985
申请日：2013-07-08
Applicant: Rambus Inc.
Inventor： Jie Shen , Yueyong Wang , James E. Harris
CPC classification number: H04N5/3355 , H04N5/2353 , H04N5/3535 , H04N5/355 , H04N5/3745 , H04N5/37455
Abstract: A self-resetting pixel having a memory element to record occurrence of an asynchronous pixel reset and circuitry to enable the memory element to be digitally sampled and cleared is disclosed, together with embodiments of digital image sensors formed by arrays or other collections of such pixels. By marking occurrence of asynchronous reset events within an in-pixel memory element that may be digitally oversampled during an exposure interval (i.e., repeatedly read-out in the form of, for example, a single-bit), it becomes possible to check for and detect asynchronous pixel reset events frequently and efficiently.
Abstract translation: 公开了具有用于记录异步像素复位的存储元件以及使存储器元件能够被数字采样和清除的电路的自复位像素，以及由这些像素的阵列或其他集合形成的数字图像传感器的实施例。 通过标记可能在曝光间隔期间被数字过采样的像素内存储元件内的异步复位事件的出现（例如，以例如单位形式重复读出），可以检查 并频繁且高效地检测异步像素复位事件。
-
公开(公告)号：US09515856B2
公开(公告)日：2016-12-06
申请号：US14720518
申请日：2015-05-22
Applicant: Rambus Inc.
Inventor： Kambiz Kaviani , Amir Amirkhany , Jason Chia-Jen Wei , Aliazam Abbasfar
CPC classification number: H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.
-
公开(公告)号：US09502096B2
公开(公告)日：2016-11-22
申请号：US14573323
申请日：2014-12-17
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C7/00 , G11C11/406 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C29/02 , G06F1/32 , G11C11/4074
CPC classification number: G11C11/40615 , G06F1/3234 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C29/022 , G11C29/028
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
-
-
-
-
-
-
-
-
-
Search Results
3867
records
(took 0.042 seconds)
