公开(公告)号：US20230252265A1

公开(公告)日：2023-08-10

申请号：US18126233

申请日：2023-03-24

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/3436 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688

Abstract: A method of scanning N×N pixels using a vector-by-matrix multiplication array by (a) associating a filter of M×M pixels adjacent first vertical and horizontal edges, (b) providing values for the pixels associated with different respective rows of the filter to input lines of different respective N input line groups, (c) shifting the filter horizontally by X pixels, (d) providing values for the pixels associated with different respective rows of the horizontally shifted filter to input lines, of different respective N input line groups, which are shifted by X input lines, (e) repeating steps (c) and (d) until a second vertical edge is reached, (f) shifting the filter horizontally to be adjacent the first vertical edge, and shifting the filter vertically by X pixels, (g) repeating steps (b) through (e) for the vertically shifted filter, and (h) repeating steps (f) and (g) until a second horizontal edge is reached.

公开(公告)号：US20230238453A1

公开(公告)日：2023-07-27

申请号：US18126954

申请日：2023-03-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  XIAN LIU ,  CHIEN-SHENG SU ,  Nhan DO ,  CHUNMING WANG

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L29/788 ,  H01L27/0705 ,  H01L29/0847 ,  H01L29/40114 ,  H01L28/00 ,  H01L29/42328 ,  H01L29/66545 ,  G11C2216/10 ,  H01L29/6653

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US20230223077A1

公开(公告)日：2023-07-13

申请号：US18124334

申请日：2023-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  H01L29/423 ,  G11C16/14 ,  H01L29/788 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C11/54 ,  H01L29/42324 ,  G11C16/14 ,  H01L29/7883 ,  H01L29/42328 ,  G11C16/10 ,  G06N3/045 ,  H10B41/30 ,  G11C16/0483

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

公开(公告)号：US20230162794A1

公开(公告)日：2023-05-25

申请号：US17588198

申请日：2022-01-28

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/0425 ,  G11C16/26 ,  H01L27/11521

Abstract: Various examples of memory systems comprising an address fault detection system are disclosed. The memory system comprises a first memory array, a row decoder, and an address fault detection system comprising a second array, wherein the row decoder decodes row addresses into word lines, each word line coupled to a row of cells in the first array and a row of cells in the second array. The second array contains digital bits and/or analog values that are used to identify address faults.

公开(公告)号：US11652162B2

公开(公告)日：2023-05-16

申请号：US17021678

申请日：2020-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L21/28 ,  H01L49/02 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L27/0705 ,  H01L28/00 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/788 ,  G11C2216/10 ,  H01L29/6653

Abstract: A simplified method for forming a non-volatile memory cell using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. An insulation block is formed on the first polysilicon layer. Spacers are formed adjacent first and second sides of the insulation block, and with the spacer adjacent the first side is reduced. Exposed portions of the first poly silicon layer are removed while maintaining a polysilicon block of the first polysilicon layer disposed under the insulation block. A second polysilicon layer is formed over the substrate and the insulation block in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed adjacent the first side of the insulation block), and a second polysilicon block (disposed adjacent the second side of the insulation block).

公开(公告)号：US11626176B2

公开(公告)日：2023-04-11

申请号：US17571443

申请日：2022-01-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Guangming Lin ,  Xiaozhou Qian ,  Xiao Yan Pi ,  Vipin Tiwari ,  Zhenlin Ding

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G06F12/02

Abstract: The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.

公开(公告)号：US20230053608A1

公开(公告)日：2023-02-23

申请号：US17519241

申请日：2021-11-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G06F3/06

Abstract: Numerous embodiments of a hybrid memory system are disclosed. The hybrid memory can store weight data in an array in analog form when used in an analog neural memory system or in digital form when used in a digital neural memory system. Input circuitry and output circuitry are capable of supporting both forms of weight data.

公开(公告)号：US11586898B2

公开(公告)日：2023-02-21

申请号：US16360733

申请日：2019-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly

IPC: G06N3/063 ,  G06N3/08 ,  G11C16/04 ,  G11C16/10 ,  G06F12/0811 ,  G11C11/4063 ,  G11C11/54

Abstract: Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.

公开(公告)号：US20230048411A1

公开(公告)日：2023-02-16

申请号：US17520396

申请日：2021-11-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  KHA NGUYEN ,  THUAN VU ,  HIEN PHAM ,  STANLEY HONG ,  STEPHEN TRINH

IPC: G06N3/063 ,  G06F17/16 ,  H03M1/46

Abstract: Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.

公开(公告)号：US11568229B2

公开(公告)日：2023-01-31

申请号：US16151259

申请日：2018-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Thuan Vu ,  Anh Ly ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/06 ,  G06F3/06 ,  G06F11/16 ,  G06N3/063

Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.