公开(公告)号：US4398338A

公开(公告)日：1983-08-16

申请号：US219784

申请日：1980-12-24

申请人： Andrew C. Tickle ,  Madhukar B. Vora

发明人： Andrew C. Tickle ,  Madhukar B. Vora

IPC分类号： H01L27/112 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/20 ,  H01L21/225

CPC分类号： H01L27/11517 ,  G11C16/0433 ,  H01L27/115

摘要： A process for fabricating an electrically erasable nonvolatile memory cell comprises forming a first region of insulating material which is less than about 200 Angstroms thick on a selected surface portion of an electrically-isolated relatively lightly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of the epitaxial pocket are exposed. Regions of the epitaxial pocket underlying the first and second exposed surface areas are doped such that first and second relatively lightly doped regions of a second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon regions of the first conductivity type are formed on the first insulating region and on the second relatively lightly doped epitaxial region. Insulating material is formed over exposed surfaces of the first polysilicon region and the second polysilicon region such that first and second surface portions of the second relatively lightly doped epitaxial region are exposed. The regions of the epitaxial pocket underlying the surface of the first relatively lightly doped epitaxial region and the first and second surface portions of the second relatively lightly doped epitaxial region are doped such that first, second and third relatively heavily doped epitaxial regions of the second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon of the second conductivity type is formed on the insulating regions covering said first conductivity type polycrystalline regions.

摘要翻译： 一种用于制造电可擦除非易失性存储单元的工艺包括在第一导电类型的外部硅的电隔离相对轻掺杂的袋的选定表面部分上形成小于约200埃厚的绝缘材料的第一区域，使得 露出外延袋的第一和第二表面区域。 在第一和第二暴露表面区域下面的外延袋的区域被掺杂，使得第二导电类型的第一和第二相对轻掺杂的区域形成在外延袋中。 在第一绝缘区域和第二相对轻掺杂的外延区域上形成第一导电类型的相对重掺杂的多晶硅区域。 绝缘材料形成在第一多晶硅区域和第二多晶硅区域的暴露表面上，使得暴露第二相对轻掺杂的外延区域的第一和第二表面部分。 在第一相对轻掺杂的外延区域的表面下面的外延阱的区域和第二相对轻掺杂的外延区域的第一和第二表面部分被掺杂，使得具有第二导电性的第一，第二和第三相对重掺杂的外延区域 类型形成在外延袋中。 在覆盖所述第一导电型多晶区域的绝缘区域上形成第二导电类型的相对重掺杂的多晶硅。

公开(公告)号：US4393473A

公开(公告)日：1983-07-12

申请号：US282893

申请日：1981-07-13

申请人： Roger V. Rufford

发明人： Roger V. Rufford

IPC分类号： G11C5/00 ,  G11C7/20 ,  G11C11/416 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C5/00 ,  G11C11/416 ,  G11C7/20

摘要： Circuitry for presetting a bipolar random access memory includes switching transistors, responsive to an applied memory preset signal, for opening the circuit between the memory word lines and their respective current sources, for applying a positive voltage to the bottom word lines, for breaking the circuitry between bit line clamping circuits and their respective power sources, and for grounding the bit line pairs to drain all current from the bit line circuits. The preset circuitry also includes read/write control transistors coupled between each bit line and a V.sub.cc source for steering the set of the memory cells upon removal of the preset signal.

摘要翻译： 用于预置双极性随机存取存储器的电路包括响应于所施加的存储器预设信号的开关晶体管，用于打开存储器字线和它们各自的电流源之间的电路，以将正电压施加到底部字线，以断开电路 位线钳位电路和它们各自的电源之间，并且用于使位线对接地，从而排除来自位线电路的所有电流。 预置电路还包括耦合在每个位线和Vcc源之间的读/写控制晶体管，用于在去除预设信号时转向存储单元组。

公开(公告)号：USRE31056E

公开(公告)日：1982-10-12

申请号：US154151

申请日：1980-05-28

申请人： Yuk B. Chau ,  George Niu ,  Rudolph Staffelbach

发明人： Yuk B. Chau ,  George Niu ,  Rudolph Staffelbach

IPC分类号： G01R31/319

CPC分类号： G01R31/31924

摘要： High-speed testing circuitry which, when coupled to one terminal of a multi-terminal electronic device, such as an integrated circuit, can either supply test stimuli signals up to a frequency of 30 MHz, receive output signals produced by the device under test in response to test stimuli signals applied by associated test circuits and compare these signals against computer predicted signals, or provide for parametric testing of the device. .Iadd.

公开(公告)号：US4351892A

公开(公告)日：1982-09-28

申请号：US260514

申请日：1981-05-04

申请人： T. Grant Davis

发明人： T. Grant Davis

IPC分类号： H01L21/027 ,  G03F9/00 ,  H01L23/544 ,  H01L21/312

CPC分类号： H01L23/544 ,  G03F9/00 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： An alignment target for an electron-beam direct write system is formed on a wafer of semiconductor material. First, a layer of silicon oxide is formed on a surface of the wafer. Then a layer of silicon nitride is formed on the oxide. Next, an opening is etched in the nitride layer to expose a surface portion of the oxide. The surface portion of the oxide is then etched to form a hole in the oxide. The hole is formed such that the oxide layer is undercut beneath the nitride layer such that a cantilevered nitride overhang is formed around the perimeter of the hole. A layer of aluminum is then deposited over the nitride layer.

摘要翻译： 在半导体材料的晶片上形成电子束直接写入系统的对准目标。 首先，在晶片的表面上形成氧化硅层。 然后在氧化物上形成一层氮化硅。 接下来，在氮化物层中蚀刻开口以暴露氧化物的表面部分。 然后蚀刻氧化物的表面部分以在氧化物中形成孔。 孔形成为使得氧化物层在氮化物层下方被切下，使得在孔的周边周围形成悬臂状氮化物突出端。 然后在氮化物层上沉积一层铝。

公开(公告)号：US4325984A

公开(公告)日：1982-04-20

申请号：US172745

申请日：1980-07-28

申请人： Christopher H. Galfo ,  Ashok L. Nalamwar

发明人： Christopher H. Galfo ,  Ashok L. Nalamwar

IPC分类号： C23F4/00 ,  C23F11/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  B05D3/04 ,  B05D3/06

CPC分类号： H01L21/02071 ,  C23F4/00

摘要： A method for preventing the post-etch corrosion of aluminum or aluminum alloy film which has been etched utilizing chlorinated plasma wherein the etched film is exposed to fluorinated plasma.

摘要翻译： 一种用于防止利用氯化等离子体蚀刻的铝或铝合金膜的蚀刻后腐蚀的方法，其中蚀刻膜暴露于氟化等离子体。

公开(公告)号：US4324216A

公开(公告)日：1982-04-13

申请号：US110736

申请日：1980-01-09

申请人： Nicky M. Johnson ,  Lawrence M. Blaser

发明人： Nicky M. Johnson ,  Lawrence M. Blaser

IPC分类号： F02P5/15 ,  F02P3/045 ,  F02P5/155 ,  F02P15/00 ,  F02P5/08 ,  F02P5/04

CPC分类号： F02P3/0456 ,  F02P15/008 ,  F02P5/155 ,  Y02T10/46

摘要： An electronic advance and ignition control system incorporating the advance utilizes a fixed advance threshold compared with amplitude of an RPM sensitive input waveform from a distributor in combination with a timing circuit, which establishes a predetermined RPM rate above which the advance operates. The electronic advance accurately duplicates the function of conventional centrifugal and vacuum and advance retard mechanisms in controlling timing of an ignition coil drive signal. The electronic advance is provided as part of an ignition control integrated circuit which can operate in a stand alone mode or share control of the ignition system with a microprocessor through interface circuits also forming part of the integrated circuit.

摘要翻译： 结合前进的电子提前和点火控制系统与定时电路组合的来自分配器的RPM敏感输入波形的振幅相比，具有固定的提前阈值，该定时电路建立预定操作之前的预定RPM速率。 电子提前准确地复制了常规离心和真空的功能，并提出了控制点火线圈驱动信号定时的延迟机制。 电子提前作为点火控制集成电路的一部分提供，该点火控制集成电路可以在独立模式下操作或者通过也构成集成电路的一部分的接口电路与微处理器共享点火系统的控制。

公开(公告)号：US4298402A

公开(公告)日：1981-11-03

申请号：US118291

申请日：1980-02-04

申请人： Hemraj K. Hingarh

发明人： Hemraj K. Hingarh

IPC分类号： H01L21/8226 ,  H01L21/033 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/73 ,  H01L29/735 ,  H01L21/265 ,  H01L21/20

CPC分类号： H01L21/32155 ,  H01L21/033 ,  H01L21/8222 ,  H01L29/735

摘要： A surface oriented lateral bipolar transistor having a base of narrow width is fabricated by using a doped polycrystalline silicon layer as an ion implantation mask when implanting ions for the emitter and base regions. In forming the doped polysilicon mask, a first layer of dopant masking material is formed on the surface of a semiconductor substrate, a second layer of undoped polysilicon is formed over the first layer, and a third layer of dopant masking material is formed over the second layer. Portions of the second and third layers are removed and a dopant is diffused into the exposed edge portion of the second layer. The third layer and the undoped portion of the second layer are then removed thereby leaving only the doped portion of the second layer on the first layer.

摘要翻译： 当为发射极和基极区域注入离子时，通过使用掺杂多晶硅层作为离子注入掩模来制造具有窄宽度基底的表面取向横向双极晶体管。 在形成掺杂多晶硅掩模时，在半导体衬底的表面上形成第一掺杂剂掩模材料层，在第一层上形成第二层未掺杂的多晶硅，在第二层上形成第三层掺杂剂掩模材料 层。 去除第二层和第三层的部分，并且掺杂剂扩散到第二层的暴露边缘部分中。 然后去除第三层和第二层的未掺杂部分，从而仅在第一层上仅留下第二层的掺杂部分。

公开(公告)号：US4289574A

公开(公告)日：1981-09-15

申请号：US157996

申请日：1980-06-09

申请人： Steven J. Radigan ,  Robert L. Berry

发明人： Steven J. Radigan ,  Robert L. Berry

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  C23F1/02

CPC分类号： H01L21/31116 ,  H01L21/033 ,  H01L21/32136 ,  Y10S438/97

摘要： A process for patterning plasma etchable regions on a semiconductor structure includes the steps of forming a layer of an oxide of aluminum over the surface of the semiconductor structure, forming an overlying layer of plasma etchable material on the layer of oxide, and removing undesired portions of the overlying layer by plasma etching to thereby expose portions of the layer of oxide. In some embodiments of the invention the thereby exposed portions of the layer of oxide are then removed, together with any underlying portions of the first layer, by isotropic etching.

摘要翻译： 用于在半导体结构上构图等离子体可蚀刻区域的工艺包括以下步骤：在半导体结构的表面上形成铝的氧化物层，在氧化层上形成等离子体可蚀刻材料的上层，并除去不期望的部分 通过等离子体蚀刻覆盖层，从而暴露氧化层的部分。 在本发明的一些实施例中，随后通过各向同性蚀刻将氧化层从而暴露出的部分与第一层的任何下面的部分一起去除。

公开(公告)号：US4624046A

公开(公告)日：1986-11-25

申请号：US770355

申请日：1985-08-27

申请人： Jay A. Shideler ,  Umeshwar D. Mishra

发明人： Jay A. Shideler ,  Umeshwar D. Mishra

IPC分类号： H01L21/762 ,  H01L21/8224 ,  H01L27/02 ,  H01L27/102 ,  H01L29/06 ,  H01L21/265 ,  H01L21/225 ,  H01L29/72

CPC分类号： H01L27/0233 ,  H01L21/7621 ,  H01L21/8224 ,  H01L27/1026 ,  H01L29/0638 ,  Y10S148/01

摘要： An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by elminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacutre PROMS from vertical NPN transistors. An LV.sub.CEO implant is used to increase the breakdown voltage of each vertical transistor from its collector-to-emitter thereby allowing junction avalanching of selected emitter-base junctions to program selected PROMs in the array even though the programming voltage is only a few volts beneath the breakdown voltage of the oxide isolated structure.

摘要翻译： 公开了一种氧化物隔离的RAM和PROM工艺，其中RAM电路包括形成在垂直NPN器件的同一岛硅材料中的横向PNP晶体管，并且还进一步与侧PNP的基极和 垂直NPN通过通过形成在相邻的半导体材料岛中的接收区域访问的埋入接触区域。 隔离氧化物之下的场注入避免了沿着邻近场氧化的半导体材料的侧壁注入杂质，因此提供了从一个硅岛到另一硅岛的垂直和横向隔离。 通过从半导体岛的侧壁排出场扩散可以获得大小尺寸和单元尺寸的显着减小。 横向PNP晶体管用作使用本发明的结构构造的存储器电路的有源负载。 该过程也可用于从垂直NPN晶体管制造PROMS。 使用LVCEO注入来增加每个垂直晶体管从其集电极到发射极的击穿电压，从而允许选择的发射极 - 基极结的接合雪崩来对阵列中的所选PROM进行编程，即使编程电压仅在几 氧化物隔离结构的击穿电压。

公开(公告)号：US4619844A

公开(公告)日：1986-10-28

申请号：US693401

申请日：1985-01-22

申请人： John M. Pierce ,  William I. Lehrer

发明人： John M. Pierce ,  William I. Lehrer

IPC分类号： C23C16/44 ,  C23C16/448 ,  C23C16/455 ,  C23C16/00 ,  B05C11/00

CPC分类号： C23C16/4485

摘要： A method of introducing a controlled flow of vapor from a high pressure sublimation chamber into a low pressure vapor deposition reactor, said vapor being derived from solid source material preferably, but not necessarily, having a vapor pressure above about one (1) Torr at a temperature not exceeding about 350.degree. C. The method comprises controllably heating the source material to a temperature sufficient to produce vapor therefrom at a desired pressure, and then controllably transferring the vapor through vapor transmission means to the vapor deposition reactor. During such transfer, the transmission means is maintained at a temperature sufficient to prevent condensation of the vapor therein during transfer. The vapor is delivered to the reactor in a pure state and is not mixed with any carrier medium.

摘要翻译： 将受控的蒸汽流从高压升华室引入低压气相沉积反应器的方法，所述蒸汽源自固体源材料，优选但不一定具有高于约一（1）乇的蒸气压， 温度不超过约350℃。该方法包括可控地将源材料加热到足以在所需压力下产生蒸汽的温度，然后通过蒸气传输装置将蒸汽可控地转移到气相沉积反应器。 在这种转移期间，传动装置保持在足以防止在传送期间蒸气冷凝的温度。 蒸汽以纯的状态输送到反应器中，并且不与任何载体介质混合。