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    Self-aligned polysilicon base contact in a bipolar junction transistor
    31.
    发明授权
    Self-aligned polysilicon base contact in a bipolar junction transistor 失效
    双极结晶体管中的自对准多晶硅基极接触

    公开(公告)号：US5581114A

    公开(公告)日：1996-12-03

    申请号：US482164

    申请日：1995-06-07

    Applicant: Rashid Bashir ,  Francois Hebert

    Inventor： Rashid Bashir ,  Francois Hebert

    IPC: H01L21/8249 ,  H01L27/082 ,  H01L27/088 ,  H01L27/102

    CPC classification number: H01L21/8249 ,  Y10S148/01 ,  Y10S257/90

    Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed. The separation between the polysilicon base contact and the polysilicon emitter is controlled by the thickness the second polysilicon layer and the thickness of the spacers so that the base contact is self-aligned with a fixed separation from the emitter. Layer and spacer thicknesses define separation between the emitter and the base contact and permit sub-micron active regions in the substrate.

    Abstract translation: 根据本发明的双极晶体管包括与多晶硅发射器（303）自对准的多晶硅基极接触（607A）。 多晶硅发射体由覆盖衬底（201）中的本征基极区（502）的第一多晶硅层形成。 衬底中的外在基极（504）与本征基极接触并且与邻近发射极的间隔物（406）自对准。 多晶硅基极接触由与外部基极接触并覆盖发射极的第二多晶硅层（407）形成。 第二侧壁间隔物（508）由发射极引起的步骤形成在第二多晶硅层上。 形成在第二多晶硅层的部分上的保护层（509,510）在第二间隔物和第二多晶硅层的下面部分被去除时保护基极接触。 多晶硅基底触点和多晶硅发射极之间的间隔由第二多晶硅层的厚度和间隔物的厚度来控制，使得基极接触件与发射极的固定分离自对准。 层和间隔物厚度限定了发射极和基极接触之间的间隔，并允许衬底中的亚微米有源区。

    Process for making self-aligned polysilicon base contact in a bipolar junction transistor
    32.
    发明授权
    Process for making self-aligned polysilicon base contact in a bipolar junction transistor 失效
    在双极结型晶体管中进行自对准多晶硅基极接触的工艺

    公开(公告)号：US5451532A

    公开(公告)日：1995-09-19

    申请号：US273530

    申请日：1994-07-11

    Applicant: Rashid Bashir ,  Francois Hebert

    Inventor： Rashid Bashir ,  Francois Hebert

    IPC: H01L21/8249 ,  H01L21/8222

    CPC classification number: H01L21/8249 ,  Y10S148/01 ,  Y10S257/90

    Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed. The separation between the polysilicon base contact and the polysilicon emitter is controlled by the thickness the second polysilicon layer and the thickness of the spacers so that the base contact is self-aligned with a fixed separation from the emitter. Layer and spacer thicknesses define separation between the emitter and the base contact and permit sub-micron active regions in the substrate.

    Abstract translation: 根据本发明的双极晶体管包括与多晶硅发射器（303）自对准的多晶硅基极接触（607A）。 多晶硅发射体由覆盖衬底（201）中的本征基极区（502）的第一多晶硅层形成。 衬底中的外在基极（504）与本征基极接触并且与邻近发射极的间隔物（406）自对准。 多晶硅基极接触由与外部基极接触并覆盖发射极的第二多晶硅层（407）形成。 第二侧壁间隔物（508）由发射极引起的步骤形成在第二多晶硅层上。 形成在第二多晶硅层的部分上的保护层（509,510）在去除第二间隔物和第二多晶硅层的下面部分时保护基极接触。 多晶硅基底触点和多晶硅发射极之间的间隔由第二多晶硅层的厚度和间隔物的厚度来控制，使得基极接触件与发射极的固定分离自对准。 层和间隔物厚度限定了发射极和基极接触之间的间隔，并允许衬底中的亚微米有源区。

    Method of making truly complementary and self-aligned bipolar and CMOS transistor structures with minimized base and gate resistances and parasitic capacitance
    33.
    发明授权
    Method of making truly complementary and self-aligned bipolar and CMOS transistor structures with minimized base and gate resistances and parasitic capacitance 失效
    制造具有最小的基极和栅极电阻和寄生电容的真正互补和自对准双极和CMOS晶体管结构的方法

    公开(公告)号：US5439833A

    公开(公告)日：1995-08-08

    申请号：US213630

    申请日：1994-03-15

    Applicant: Francois Hebert ,  Datong Chen ,  Rashid Bashir

    Inventor： Francois Hebert ,  Datong Chen ,  Rashid Bashir

    IPC: H01L21/8249 ,  H01L27/06 ,  H01L21/265

    CPC classification number: H01L27/0623 ,  H01L21/8249 ,  Y10S148/009

    Abstract: A truly complementary bipolar transistor structure and a combined bipolar and CMOS transistor structure are disclosed, each including a silicide layer formed upon a substrate that acts as an extrinsic base and gate. Optionally, a layer of polysilicon can be formed between the silicide layer and the substrate. An oxide layer (LTO) is formed or deposited over the silicide layer by chemical vapor deposition (CVD). Selected regions are defined and etched using a photoresist layer. Subsequent steps of implanting, etching and metalization are performed to produce transistors with reduced gate and extrinsic base resistances. Polysilicon may be used, instead of metal, as a contact in one embodiment of the invention.

    Abstract translation: 公开了一种真正互补的双极晶体管结构和组合的双极和CMOS晶体管结构，每个晶体管结构包括形成在用作外部基极和栅极的衬底上的硅化物层。 可选地，可以在硅化物层和衬底之间形成多晶硅层。 通过化学气相沉积（CVD）在硅化物层上形成或沉积氧化物层（LTO）。 使用光致抗蚀剂层限定和蚀刻所选择的区域。 进行植入，蚀刻和金属化的后续步骤以产生具有减小的栅极和非本征基极电阻的晶体管。 在本发明的一个实施方案中，可以使用多晶硅代替金属作为接触。

    Systems and methods for forming isolated devices in a handle wafer
    34.
    发明授权
    Systems and methods for forming isolated devices in a handle wafer 有权
    在处理晶片中形成隔离器件的系统和方法

    公开(公告)号：US09257525B2

    公开(公告)日：2016-02-09

    申请号：US13283139

    申请日：2011-10-27

    Applicant: I-Shan Sun ,  Rick Carlton Jerome ,  Francois Hebert

    Inventor： I-Shan Sun ,  Rick Carlton Jerome ,  Francois Hebert

    IPC: H01L21/00 ,  H01L29/66 ,  H01L23/48 ,  H01L23/535 ,  H01L21/74 ,  H01L27/06

    CPC classification number: H01L29/66204 ,  H01L21/743 ,  H01L23/481 ,  H01L23/535 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.

    Abstract translation: 提供了一种通过积分硅通过集成的方法。 该方法包括在处理晶片中形成电气装置。 该方法还包括在手柄晶片和电气装置上形成隔离层，并将活性层连接到隔离层。 此外，该方法包括通过有源层和隔离层形成至少一个沟槽，以暴露处理晶片的一部分并在至少一个沟槽中沉积导电材料，导电材料提供与电 设备通过活动层。

    SCHOTTKY DIODE WITH COMBINED FIELD PLATE AND GUARD RING
    37.
    发明申请
    SCHOTTKY DIODE WITH COMBINED FIELD PLATE AND GUARD RING 审中-公开
    肖特基二极管与组合的现场板和保护环

    公开(公告)号：US20120007097A1

    公开(公告)日：2012-01-12

    申请号：US12944163

    申请日：2010-11-11

    Applicant: Francois Hebert

    Inventor： Francois Hebert

    IPC: H01L29/20 ,  H01L29/872 ,  H01L21/329

    CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66143

    Abstract: A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate.

    Abstract translation: 提供了包括合并的保护环和限定肖特基接触区域的场板的肖特基二极管。 肖特基金属至少部分地形成在肖特基接触区域上并且至少部分地在合并的保护环和场板上形成。

    PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD
    38.
    发明申请
    PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD 有权
    平面电力电力电感器结构与方法

    公开(公告)号：US20110107589A1

    公开(公告)日：2011-05-12

    申请号：US13007551

    申请日：2011-01-14

    Applicant: Francois Hebert ,  Tao Feng ,  Jun Lu

    Inventor： Francois Hebert ,  Tao Feng ,  Jun Lu

    IPC: H01F7/06

    CPC classification number: H01F17/0033 ,  H01F1/344 ,  H01F41/046 ,  H01F2017/002 ,  Y10T29/4902

    Abstract: An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

    Abstract translation: 电感器可以包括平面铁氧体磁芯。 第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。 在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。 第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。 第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。 每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。 导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

    PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD
    39.
    发明申请
    PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD 有权
    平面电力电力电感器结构与方法

    公开(公告)号：US20090322461A1

    公开(公告)日：2009-12-31

    申请号：US12165423

    申请日：2008-06-30

    Applicant: Francois Hebert ,  Tao Feng ,  Jun Lu

    Inventor： Francois Hebert ,  Tao Feng ,  Jun Lu

    IPC: H01F27/02

    CPC classification number: H01F17/0033 ,  H01F1/344 ,  H01F41/046 ,  H01F2017/002 ,  Y10T29/4902

    Abstract: An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

    Abstract translation: 电感器可以包括平面铁氧体磁芯。 第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。 在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。 第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。 第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。 每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。 导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

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