公开(公告)号：US07362651B2

公开(公告)日：2008-04-22

申请号：US11383023

申请日：2006-05-12

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G11C8/00

CPC classification number: G11C5/063 ,  G11C7/1048 ,  G11C7/1066

Abstract: A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.

Abstract translation: 双数据速率两同步动态随机存取（DDR2）存储器电路包括低速输入路径和通过输入耦合耦合到其上的高速输入路径并形成公共输入，公共输入耦合到存储器核心 存储器芯具有公共输出，其中高速输出路径和低速输出路径通过输出耦合耦合在一起并进一步耦合到存储器核心的公共输出端。

公开(公告)号：US6054749A

公开(公告)日：2000-04-25

申请号：US299047

申请日：1999-04-23

Applicant: Gerald K. Bartley ,  Peter A. Franklin ,  Carmine J. Mele ,  Arthur G. Merryman ,  John R. Pennacchia ,  Kurt A. Smith ,  Thomas A. Wassick ,  Thomas A. Wayson ,  Roy Yu

Inventor： Gerald K. Bartley ,  Peter A. Franklin ,  Carmine J. Mele ,  Arthur G. Merryman ,  John R. Pennacchia ,  Kurt A. Smith ,  Thomas A. Wassick ,  Thomas A. Wayson ,  Roy Yu

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/538 ,  H05K3/22 ,  H01L27/02 ,  H01L27/10

CPC classification number: H01L21/485 ,  H01L21/76892 ,  H01L23/5382 ,  H05K3/225 ,  H01L2924/0002

Abstract: A process for partially repairing defective Multi-Chip Module (MCM) Thin-Film (TF) wiring nets. The process comprises the steps of locating a short circuit between any two nets of the MCM, identifying a site to cut in one of the two nets, and deleting an internal portion of one of the two nets at the identified site.

Abstract translation: 部分修复有缺陷的多芯片模块（MCM）薄膜（TF）布线网的过程。 该过程包括以下步骤：在MCM的任何两个网络之间定位短路，识别在两个网络中的一个网络中切割的站点，以及删除所识别的站点上的两个网络中的一个网络的内部部分。

公开(公告)号：US5972723A

公开(公告)日：1999-10-26

申请号：US955204

申请日：1997-10-21

Applicant: Gerald K. Bartley ,  Peter A. Franklin ,  Carmine J. Mele ,  Arthur G. Merryman ,  John R. Pennacchia ,  Kurt A. Smith ,  Thomas A. Wassick ,  Thomas A. Wayson ,  Roy Yu

Inventor： Gerald K. Bartley ,  Peter A. Franklin ,  Carmine J. Mele ,  Arthur G. Merryman ,  John R. Pennacchia ,  Kurt A. Smith ,  Thomas A. Wassick ,  Thomas A. Wayson ,  Roy Yu

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/538 ,  H05K3/22 ,  H01L21/00

CPC classification number: H01L21/485 ,  H01L21/76892 ,  H01L23/5382 ,  H05K3/225 ,  H01L2924/0002

Abstract: A process for partially repairing defective Multi-Chip Module (MCM) Thin-Film (TF) wiring nets. The process comprises the steps of locating a short circuit between any two nets of the MCM, identifying a site to cut in one of the two nets, and deleting an internal portion of one of the two nets at the identified site.

Abstract translation: 部分修复有缺陷的多芯片模块（MCM）薄膜（TF）布线网的过程。 该过程包括以下步骤：在MCM的任何两个网络之间定位短路，识别在两个网络中的一个网络中切割的站点，以及删除所识别的站点上的两个网络中的一个网络的内部部分。

公开(公告)号：US5763947A

公开(公告)日：1998-06-09

申请号：US594201

申请日：1996-01-31

Applicant: Gerald K. Bartley

Inventor： Gerald K. Bartley

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L23/053 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5382 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: An integrated circuit chip package having an electrical contact configurable for either signal or power/ground and a method for constructing the integrated circuit chip package are disclosed. The integrated circuit chip package includes a substrate for supporting an integrated circuit chip and a dedicated conductor for supplying voltage to the integrated circuit chip. A configurable contact is attached to a surface of the substrate. The integrated circuit chip package further includes a signal connection for electrically connecting a signal connector of an integrated circuit chip and the configurable contact. A removable connector electrically connects the configurable contact and the dedicated conductor, thereby enabling the configurable contact to be configured as either a signal or power/ground contact depending upon the absence or presence of the electrical connection between the configurable contact and the dedicated conductor provided by the removable connector.

Abstract translation: 公开了一种具有可配置用于信号或电源/接地的电接触的集成电路芯片封装以及用于构建集成电路芯片封装的方法。 集成电路芯片封装包括用于支撑集成电路芯片的基板和用于向集成电路芯片提供电压的专用导体。 可配置触点附着到基板的表面。 集成电路芯片封装还包括用于电连接集成电路芯片的信号连接器和可配置触点的信号连接。 可移动连接器将可配置触点和专用导体电连接，从而使可配置触点被配置为信号或电源/接地触点，这取决于可配置触点和专用导体之间的电连接的不存在或存在， 可移动连接器。

公开(公告)号：US09003559B2

公开(公告)日：2015-04-07

申请号：US12181357

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Carl-Otto Nilsen

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Carl-Otto Nilsen

IPC: G06F1/26 ,  G06F11/00 ,  G08B13/00 ,  G08B21/00 ,  G08B29/00 ,  G06F21/87

CPC classification number: G06F21/87

Abstract: Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

Abstract translation: 装置，方法和程序产品通过确定包括一个或多个连接的电路径和连接到微芯片的背面的金属板已经断开或以其他方式改变来检测试图篡改微芯片。 响应于不可能存在的电路径的存在，也可以检测到篡改尝试，这可能是因为微芯片被错误地重新构成。 可以自动选择和监视实际和/或欺骗性路径，以进一步混淆反向工程尝试。

公开(公告)号：US20140070393A1

公开(公告)日：2014-03-13

申请号：US13613564

申请日：2012-09-13

Applicant: Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Gerald K. Bartley ,  Charles L. Johnson ,  John E. Kelly, III ,  Joseph Kuczynski ,  David R. Motschman ,  Arvind K. Sinha ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: H01L23/367 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L21/02656 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/4275 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/10165 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83909 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip

Abstract translation: 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括放置在第一芯片和第二芯片之间的热界面材料垫，其中热界面材料垫包括平行于第一芯片和第二芯片的配合表面排列的纳米纤维，并且纳米纤维垂直于第一芯片和第二芯片的配合表面对齐 芯片和第二芯片

公开(公告)号：US08492903B2

公开(公告)日：2013-07-23

申请号：US13171919

申请日：2011-06-29

Applicant: Gerald K. Bartley ,  Philip R. Germann ,  David P. Paulsen ,  John E. Sheets, II

Inventor： Gerald K. Bartley ,  Philip R. Germann ,  David P. Paulsen ,  John E. Sheets, II

IPC: H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A system comprises a first integrated circuit (IC) chip that includes a first electronic component; a second IC chip that includes a second electronic component; a through silicon via (TSV) in the second IC chip that electrically couples the first electronic component to the second electronic component; and a signal gating transistor that fully occludes the TSV.

Abstract translation: 一种系统包括：第一集成电路（IC）芯片，其包括第一电子部件; 包括第二电子部件的第二IC芯片; 在所述第二IC芯片中的通过硅通孔（TSV）将所述第一电子部件电耦合到所述第二电子部件; 以及完全封闭TSV的信号门控晶体管。

公开(公告)号：US08466024B2

公开(公告)日：2013-06-18

申请号：US12966303

申请日：2010-12-13

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Philip R. Germann ,  Andrew B. Maki ,  John E. Sheets, II

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Philip R. Germann ,  Andrew B. Maki ,  John E. Sheets, II

IPC: H01L21/336

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823437 ,  H01L23/481 ,  H01L29/785 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2924/014

Abstract: A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.

Abstract translation: 半导体芯片具有选通硅通孔（TSVG）。 可以切换TSVG，使得TSVG可以导通或不导通。 半导体芯片可以在下位半导体芯片和较高半导体芯片之间使用，以控制下位半导体芯片上的电压供应是连接到上级半导体芯片中的电压域还是与其断开。 TSVG包括由下级芯片作为开关控制的FET。

公开(公告)号：US20130001676A1

公开(公告)日：2013-01-03

申请号：US13171919

申请日：2011-06-29

Applicant: GERALD K. BARTLEY ,  PHILIP R. GERMANN ,  DAVID P. PAULSEN ,  JOHN E. SHEETS, II

Inventor： GERALD K. BARTLEY ,  PHILIP R. GERMANN ,  DAVID P. PAULSEN ,  JOHN E. SHEETS, II

IPC: H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A system comprises a first integrated circuit (IC) chip that includes a first electronic component; a second IC chip that includes a second electronic component; a through silicon via (TSV) in the second IC chip that electrically couples the first electronic component to the second electronic component; and a signal gating transistor that fully occludes the TSV.

Abstract translation: 一种系统包括：第一集成电路（IC）芯片，其包括第一电子部件; 包括第二电子部件的第二IC芯片; 在所述第二IC芯片中的通过硅通孔（TSV）将所述第一电子部件电耦合到所述第二电子部件; 以及完全封闭TSV的信号门控晶体管。

公开(公告)号：US08330489B2

公开(公告)日：2012-12-11

申请号：US12431259

申请日：2009-04-28

Applicant: Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

Inventor： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

IPC: H01L25/00

CPC classification number: G06F17/5068 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.

Abstract translation: 电路布置和方法利用多层半导体堆叠中的通用的标准化层间互连，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。 多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气 布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。 基于每个电路层中的层间界面区域的标准化布置以及与层间总线相关联的电导体的标准化布置，每个电路层可以使用标准化模板来设计，在该模板上设计实现 已经提供了层间总线，从而简化了电路层设计和功能单元与层间总线的互连。 此外，可以在半导体堆叠内定义垂直取向的超节点，以提供多个独立运行的节点，其具有布置在堆叠的多个电路层中的功能单元。