公开(公告)号：US06432820B1

公开(公告)日：2002-08-13

申请号：US09921165

申请日：2001-08-02

Applicant: Myoung-bum Lee ,  Jong-myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

Inventor： Myoung-bum Lee ,  Jong-myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

IPC: H01L2144

CPC classification number: H01L21/76856 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76888 ,  H01L2221/1089

Abstract: A method is provided for forming a metal wiring layer of a semiconductor device, which is performed in an airtight space, the pressure of which is maintained below atmospheric pressure, to form a metal deposition prevention layer. An interlayer dielectric layer pattern is formed on a semiconductor substrate so as to define a hole region. A metal film is formed on the top surface of the interlayer dielectric layer pattern under a vacuum state so as to expose the side walls of the hole region. The metal layer is oxidized in the airtight space, the pressure of which is maintained below atmospheric pressure in an oxygen atmosphere, thereby forming a metal deposition prevention layer. A metal liner is selectively formed at the side walls of the hole region. A metal layer is formed inside the hole region defined by the metal liner and on the metal deposition prevention layer. The metal liner is heat-treated and reflowed.

Abstract translation: 提供了一种用于形成半导体器件的金属布线层的方法，该方法是在压力保持在大气压以下的气密空间中进行，以形成金属沉积防止层。 在半导体衬底上形成层间绝缘层图案，以限定一个孔区。 在真空状态下在层间电介质层图案的顶表面上形成金属膜，以露出孔区域的侧壁。 金属层在气氛中被氧化，其压力在氧气氛中保持低于大气压，从而形成金属沉积防止层。 在孔区域的侧壁上选择性地形成金属衬垫。 在由金属衬垫和金属沉积防止层限定的孔区域内形成金属层。 金属衬垫被热处理和回流。

公开(公告)号：US6010940A

公开(公告)日：2000-01-04

申请号：US935464

申请日：1997-09-24

Applicant: Myoung-bum Lee ,  Hyeon-deok Lee

Inventor： Myoung-bum Lee ,  Hyeon-deok Lee

IPC: H01L21/8242 ,  C23C16/34 ,  C23C16/56 ,  H01L21/02 ,  H01L21/285 ,  H01L29/92

CPC classification number: H01L28/56 ,  C23C16/34 ,  C23C16/56 ,  H01L21/28568

Abstract: A method of fabricating a capacitor for a integrated circuit device includes the steps of forming a lower capacitor electrode on an integrated circuit substrate, and forming a dielectric layer on the lower capacitor electrode opposite the integrated circuit substrate. A titanium nitride barrier layer is deposited by chemical vapor deposition on the dielectric layer opposite the integrated circuit substrate to a thickness in the range of 50 .ANG. to 500 .ANG. using TiCl.sub.4 as a source gas. The titanium nitride barrier layer is annealed, and an upper electrode is formed on the titanium nitride barrier layer opposite the integrated circuit substrate.

Abstract translation: 一种制造用于集成电路器件的电容器的方法包括以下步骤：在集成电路衬底上形成下电容器电极，并在与集成电路衬底相对的下电容器电极上形成电介质层。 通过化学气相沉积将氮化钛阻挡层沉积在与集成电路衬底相对的电介质层上，使用TiCl 4作为源气体，其厚度范围为50纳米至500埃。 退火氮化钛阻挡层，在与集成电路基板相对的氮化钛阻挡层上形成上电极。

公开(公告)号：US5560778A

公开(公告)日：1996-10-01

申请号：US465015

申请日：1995-06-05

Applicant: In-Seon Park ,  Myoung-Bum Lee ,  Chang-Gee Hong ,  Chang-Gyu Kim ,  U-In Chung

Inventor： In-Seon Park ,  Myoung-Bum Lee ,  Chang-Gee Hong ,  Chang-Gyu Kim ,  U-In Chung

IPC: H01L21/205 ,  C23C16/02 ,  C23C16/40 ,  C23C16/44 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  C23C16/00

CPC classification number: H01L21/02164 ,  C23C16/0245 ,  C23C16/402 ,  C23C16/44 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/31051 ,  H01L21/31608

Abstract: A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.

Abstract translation: 介电材料的沉积速率随着下层的电极性而变化，以获得优异的沉积和平坦化特性。 导电层和下面的电介质被表面处理以具有不同的电极性，使得通过使用电介质材料在导电层上和在下面的电介质之间的沉积速率的差异来形成电介质。 提供了一种具有连接在基座和其气体注入部分之间的直流电源的CVD装置。 沉积和平坦化可以在低温下进行并且在工艺上被简化。

公开(公告)号：US20140070300A1

公开(公告)日：2014-03-13

申请号：US13724187

申请日：2012-12-21

Applicant: Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

Inventor： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract translation: 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

公开(公告)号：US20120061763A1

公开(公告)日：2012-03-15

申请号：US13224427

申请日：2011-09-02

Applicant: Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

Inventor： Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L21/764 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

Abstract translation: 可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。 可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。 可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。 然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

公开(公告)号：US20110303970A1

公开(公告)日：2011-12-15

申请号：US13104377

申请日：2011-05-10

Applicant: Jin-Gyun Kim ,  Myoung-Bum Lee

Inventor： Jin-Gyun Kim ,  Myoung-Bum Lee

IPC: H01L29/792

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.

Abstract translation: 垂直半导体器件和制造垂直半导体器件的方法包括形成在衬底上的第一半导体图案和形成在第一半导体图案的侧壁上的第一栅极结构。 在第一半导体图案上形成第二半导体图案。 在第二半导体图案的侧壁上形成多个绝缘层间图案。 绝缘层间图案彼此间隔开以限定绝缘层间图案之间的凹槽。 多个第二栅极结构分别设置在槽中。

公开(公告)号：US20110237055A1

公开(公告)日：2011-09-29

申请号：US13053291

申请日：2011-03-22

Applicant: Yong-hoon Son ,  Si-Young Choi ,  Myoung-Bum Lee ,  Ki-Hyun Hwang ,  Seung-Jae Baik ,  Jeong Hee Han

Inventor： Yong-hoon Son ,  Si-Young Choi ,  Myoung-Bum Lee ,  Ki-Hyun Hwang ,  Seung-Jae Baik ,  Jeong Hee Han

IPC: H01L21/20

CPC classification number: H01L27/11578 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1207

Abstract: A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer.

Abstract translation: 通过在下部存储层上形成绝缘层，在绝缘层的一部分形成单晶半导体，可靠的叠层型半导体装置。 一种制造叠层半导体器件的方法，包括：提供包括多个下部存储结构的下部存储层; 在下部存储层上形成绝缘层; 通过去除绝缘层的部分形成沟槽; 形成用于填充沟槽的准备半导体层; 以及通过相变所述预备半导体层来形成单晶半导体层。

公开(公告)号：US20110199804A1

公开(公告)日：2011-08-18

申请号：US12981625

申请日：2010-12-30

Applicant: Yong-Hoon SON ,  Myoung Bum LEE ,  Ki Hyun HWANG ,  Seung Jae BAIK

Inventor： Yong-Hoon SON ,  Myoung Bum LEE ,  Ki Hyun HWANG ,  Seung Jae BAIK

IPC: G11C5/06 ,  H01L27/08

CPC classification number: H01L27/11551 ,  G11C5/04 ,  G11C5/063 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.

Abstract translation: 三维半导体器件包括在基板上二维布置的有源图案，三维地布置在有源图案之间的电极以及三维地布置在由有源图案和电极限定的交叉点处的存储区域。 每个有源图案用作用于与形成在与基板相同的高度处的两个不同存储区域的电连接的公共电流路径。

公开(公告)号：US06602782B2

公开(公告)日：2003-08-05

申请号：US09862937

申请日：2001-05-22

Applicant: Myoung-bum Lee ,  Jong-Myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

Inventor： Myoung-bum Lee ,  Jong-Myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

IPC: H01L2144

CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76864 ,  H01L21/76876 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a metal interconnects include forming an electrically insulating layer having a contact hole therein, on a substrate. A step is also performed to form an electrically conductive seed layer. The seed layer extends on a sidewall of the contact hole and on a portion of an upper surface of the electrically insulating layer extending adjacent the contact hole. The seed layer is sufficiently thick along an upper portion of the sidewall and sufficiently thin along a lower portion of the sidewall that an upper portion of the contact hole is partially constricted by the seed layer and a constricted contact hole is thereby defined. An anti-nucleation layer is deposited on a portion of the seed layer that extends outside the constricted contact hole. The constricted contact hole is used as a mask to inhibit deposition of the anti-nucleation layer adjacent a bottom of the constricted contact hole. A metal liner is then formed on a portion of the electrically conductive seed layer that defines a sidewall of the constricted contact hole. Next, a metal interconnect layer is reflowed into the constricted contact hole to thereby fill and bury the contact hole.

Abstract translation: 形成金属互连的方法包括在基板上形成其中具有接触孔的电绝缘层。 还进行步骤以形成导电种子层。 种子层在接触孔的侧壁上延伸，并且在邻近接触孔延伸的电绝缘层的上表面的一部分上延伸。 种子层沿着侧壁的上部足够厚，并且沿着侧壁的下部足够薄，接触孔的上部被种子层部分地收缩，从而限定了收缩的接触孔。 在种子层的在收缩的接触孔外延伸的部分上沉积抗成核层。 收缩的接触孔用作掩模以抑制邻接于缩小的接触孔的底部的防着色层的沉积。 然后在导电种子层的限定收缩的接触孔的侧壁的部分上形成金属衬垫。 接下来，将金属互连层回流到收缩的接触孔中，从而填充并埋入接触孔。

公开(公告)号：US06586340B2

公开(公告)日：2003-07-01

申请号：US10098029

申请日：2002-03-13

Applicant: Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

Inventor： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

IPC: H01L21302

CPC classification number: H01L21/67167 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/67739 ,  H01L21/76882 ,  H01L21/76888 ,  Y10S438/974

Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.