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    Capacitor
    31.
    发明授权
    Capacitor 有权

    公开(公告)号：US09773618B2

    公开(公告)日：2017-09-26

    申请号：US14831964

    申请日：2015-08-21

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Tae Hwan Song

    IPC: H01G4/30 ,  H01G4/12 ,  H01G4/38 ,  H01G4/005 ,  H01G4/012 ,  H01G4/228

    CPC classification number: H01G4/30 ,  H01G4/005 ,  H01G4/012 ,  H01G4/12 ,  H01G4/228 ,  H01G4/38

    Abstract: The present invention relates to a capacitor. The capacitor includes a substrate; a dielectric layer formed on the substrate; and an electrode layer comprising a first electrode layer and a second electrode layer formed on the dielectric layer, wherein the first electrode layer and the second electrode layer are separated from each other, and at least a portion of the first electrode layer and at least a portion of the second electrode layer are disposed on a same surface. With this configuration, applying the electricity becomes easy, and since the first and the second electrode layers function as the electrodes being charged with different polarity electrical charges respectively, manufacturing thereof becomes easy, and the structure thereof is simple.

    CHIP SUBSTRATE
    33.
    发明申请
    CHIP SUBSTRATE 有权

    公开(公告)号：US20170162754A1

    公开(公告)日：2017-06-08

    申请号：US15363261

    申请日：2016-11-29

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Bum Mo AHN ,  Seung Ho PARK ,  Tae Hwan SONG

    IPC: H01L33/48

    CPC classification number: H01L33/486 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2924/00014

    Abstract: A chip substrate includes conductive layers, an insulation layer configured to electrically isolate the conductive layers, and a cavity composed of a groove formed at a predetermined depth in a region including the insulation layer. One side of the cavity includes a first surface and a second surface continuously extending from the first surface, the first surface is formed to vertically extend from a lower portion of the cavity and the second surface is formed so as to have the same slope as the other side of the cavity, whereby the distance between one side of the lower portion of the cavity and the insulation layer is increased.

    Chip substrate comprising a groove portion and chip package using the chip substrate
    34.
    发明授权
    Chip substrate comprising a groove portion and chip package using the chip substrate 有权

    公开(公告)号：US09653664B2

    公开(公告)日：2017-05-16

    申请号：US14753915

    申请日：2015-06-29

    Applicant: Point Engineering Co., Ltd.

    Inventor： Sin Seok Han ,  Soo Young Choi ,  Ki Myung Nam

    IPC: H01L29/22 ,  H01L33/58 ,  H01L33/48 ,  H01L33/62 ,  H05K1/03 ,  H05K1/02

    CPC classification number: H01L33/58 ,  H01L33/44 ,  H01L33/486 ,  H01L33/62

    Abstract: Disclosed is a chip substrate. The chip substrate includes: conductive portions laminated in one direction to constitute the chip substrate; insulation portions alternately laminated with the conductive portions to electrically isolate the conductive portions; a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate; and a groove portion disposed outside the cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape. According to the present invention, an adhesive agent is applied in a groove portion formed in advance. It is therefore possible to prevent the adhesive agent from being exposed to the light emitted from optical elements and to prevent the adhesive agent from being denatured. This makes it possible to enhance the reliability of lens bonding. Furthermore, there is no need to use an expensive resistant adhesive agent. An existing typical adhesive agent may be used as it is. This provides an effect of saving costs. Thus, there is an advantage in that a low-priced existing bonding material may be applied to a high-priced UV-C (deep-UV) package.

    CHIP SUBSTRATE COMPRISING A PLATED LAYER AND CHIP PACKAGE USING THE SAME
    35.
    发明申请
    CHIP SUBSTRATE COMPRISING A PLATED LAYER AND CHIP PACKAGE USING THE SAME 有权
    包装层的芯片基板和使用其的芯片封装

    公开(公告)号：US20160380159A1

    公开(公告)日：2016-12-29

    申请号：US14753869

    申请日：2015-06-29

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Ki Myung NAM ,  Young Woon JEON ,  Kyoung Ja YUN

    IPC: H01L33/48 ,  H01L33/54 ,  H01L33/62 ,  H01L33/58

    CPC classification number: H01L33/486 ,  H01L33/44 ,  H01L33/483 ,  H01L33/54 ,  H01L33/58 ,  H01L33/62 ,  H01L2933/0025 ,  H01L2933/0033 ,  H01L2933/0066

    Abstract: A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.

    Abstract translation: 芯片基板包括层叠导电部分和层叠绝缘部分，其将导电部分与在芯片基板的上表面上包括绝缘部分的区域中的凹陷形状的腔体电隔离。 基板包括在上表面上的不包括空腔的区域的绝缘层，以及沿着绝缘层上的芯片基板的周边的连续镀层。 每个绝缘部分的顶表面的一部分暴露在空腔中，并且每个绝缘部分的顶表面的另一部分涂覆有绝缘层。 芯片封装包括芯片基板，光学元件通过密封构件或透镜密封在空腔中。

    Micro Heater and Micro Sensor
    36.
    发明申请
    Micro Heater and Micro Sensor 审中-公开
    微加热器和微型传感器

    公开(公告)号：US20160370336A1

    公开(公告)日：2016-12-22

    申请号：US15181976

    申请日：2016-06-14

    Applicant: Point Engineering Co., Ltd.

    Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Sung Hyun Byun

    IPC: G01N33/00 ,  H05B3/03 ,  H05B3/24 ,  H05B1/02

    CPC classification number: G01N33/0027 ,  G01N27/121 ,  G01N27/128 ,  H05B1/0247 ,  H05B3/03 ,  H05B3/24

    Abstract: A micro heater includes a substrate and a heater electrode formed on the substrate. The substrate includes a plurality of pores formed to vertically extend through the substrate. A micro sensor includes a substrate, a sensor electrode formed on the substrate, and a heater electrode formed on the substrate. A protective layer may be used to protect any of the electrodes against oxidation. Any of the electrodes may be formed on a barrier layer positioned on the porous layer.

    Abstract translation: 微加热器包括形成在基板上的基板和加热电极。 衬底包括形成为垂直延伸穿过衬底的多个孔。 微型传感器包括基板，形成在基板上的传感器电极和形成在基板上的加热电极。 可以使用保护层来保护任何电极免受氧化。 任何电极可以形成在位于多孔层上的阻挡层上。

    Method for mounting a chip and chip package
    38.
    发明授权
    Method for mounting a chip and chip package 有权
    安装芯片和芯片封装的方法

    公开(公告)号：US09378986B2

    公开(公告)日：2016-06-28

    申请号：US14511353

    申请日：2014-10-10

    Applicant: Point Engineering Co., Ltd.

    Inventor： Bum Mo Ahn ,  Ki Myung Nam ,  Seung Ho Park

    IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48

    CPC classification number: H01L21/563 ,  H01L21/4825 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/562 ,  H01L24/11 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1134 ,  H01L2224/1183 ,  H01L2224/13144 ,  H01L2224/291 ,  H01L2224/32013 ,  H01L2224/32227 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83815 ,  H01L2224/92227 ,  H01L2924/12041 ,  H01L2924/15156 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

    Abstract: Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the. In addition, cracking due to the difference of thermal expansion coefficient between solder materials can be prevented by sealing the bonding portion of the chip using the solder materials. Further, since oxidation of the bonding portion is prevented by blocking the contact with the outside, the chip packaging process can be performed without an additional process of filling an inert gas into the internal space wherein the chip is mounted.

    Abstract translation: 提供了一种安装芯片的方法。 该方法包括：在衬底的内部方向上凹入地形成的空腔的一个表面上形成凸块; 执行压印工艺以平坦化凸块的表面; 在经过压印加工的凸块上涂覆焊料; 并且通过熔化焊料材料来接合芯片和凸块，其中在芯片的底部上形成电极部分或金属部分。 对于根据本发明的金属基板，其中包括垂直绝缘层，由于芯片的电极部分和基板的电极部分必须电连接，金属基板被接合到芯片的电极部分 使用另外形成在金属基板上的凸块，使得芯片中产生的热量可以快速转移到基板，并且可以降低芯片的结温，从而提高光效率。 此外，通过使用焊料材料密封芯片的接合部分，可以防止由于焊料材料之间的热膨胀系数的差异导致的破裂。 此外，由于通过阻挡与外部的接触来防止接合部的氧化，所以可以进行芯片封装处理，而不需要在安装芯片的内部空间中填充惰性气体的附加处理。

    Chip Substrate Comprising Cavity with Curved Surfaces
    39.
    发明申请
    Chip Substrate Comprising Cavity with Curved Surfaces 有权
    包括具有弯曲表面的腔的芯片衬底

    公开(公告)号：US20160095222A1

    公开(公告)日：2016-03-31

    申请号：US14866073

    申请日：2015-09-25

    Applicant: Point Engineering Co., Ltd.

    Inventor： Seung Ho Park ,  Tae Hwan Song ,  Sung Hyun Byun

    IPC: H05K1/18 ,  H05K1/02

    CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L33/60 ,  H05K1/05 ,  H05K1/185 ,  H05K2201/09745 ,  H05K2201/10106

    Abstract: A chip substrate includes conductive portions, an insulation portion and a cavity. The conductive portions are laminated in one direction to constitute the chip substrate. The insulation portion is interposed between the conductive portions to electrically isolate the conductive portions. The cavity is formed on an upper surface of the chip substrate at a predetermined depth in a region including the insulation portion. The cavity is defined by a plurality of continuously-extending curved surfaces having predetermined radii of curvature.

    Abstract translation: 芯片基板包括导电部分，绝缘部分和空腔。 导电部分沿一个方向层叠以构成芯片基板。 绝缘部分介于导电部分之间，以使导电部分电隔离。 在包括绝缘部分的区域中，在芯片基板的上表面上以预定的深度形成空腔。 空腔由具有预定曲率半径的多个连续延伸的弯曲表面限定。

    FOLDING TYPE CAPACITOR COMPRISING THROUGH HOLE
    40.
    发明申请
    FOLDING TYPE CAPACITOR COMPRISING THROUGH HOLE 有权
    折叠式电容器包括通孔

    公开(公告)号：US20160049251A1

    公开(公告)日：2016-02-18

    申请号：US14825538

    申请日：2015-08-13

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Bum Mo AHN ,  Seung Ho PARK

    IPC: H01G4/26 ,  H01G4/06 ,  H01G4/005 ,  H01G4/30

    CPC classification number: H01G4/26 ,  H01G4/005 ,  H01G4/10 ,  H01G4/30 ,  H01G4/38

    Abstract: A folding type capacitor includes a metal substrate wherein a through hole penetrates an inside thereof; at least one dielectric layer formed on a surface of the metal substrate and an inner peripheral surface of the through hole; and an electrode layer formed on the at least one dielectric layer, wherein the metal substrate has bending portions whose surfaces are facing each other. Thus, manufacturing process is more simplified since Al2O3 insulation layers are formed by anodizing the aluminum layer without forming the extra dielectric layers after forming the aluminum layer, so that the manufacturing cost can be reduced, and also a multi-stacked capacitor having a high capacitance and a high reliability can be provided by stacking capacitors including a plurality of aluminum oxide layers using a more simplified process.

    Abstract translation: 折叠式电容器包括：金属基板，其中通孔穿透其内部; 形成在所述金属基板的表面上的至少一个电介质层和所述通孔的内周面; 以及形成在所述至少一个电介质层上的电极层，其中所述金属基板具有表面彼此相对的弯曲部。 因此，制造工艺更加简化，因为通过在形成铝层之后不形成额外的电介质层来阳极氧化铝层来形成Al 2 O 3绝缘层，从而可以降低制造成本，并且还具有高电容的多层电容器 并且可以通过使用更简化的工艺堆叠包括多个氧化铝层的电容器来提供高可靠性。

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