公开(公告)号：US06867481B2

公开(公告)日：2005-03-15

申请号：US10411688

申请日：2003-04-11

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/60 ,  H01L23/495 ,  H01L23/28

CPC classification number: H01L24/40 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，管芯封装包括包括第一表面和第二表面的半导体管芯，以及具有管芯附着区域的引线框架结构以及远离管芯附着区域延伸的多个引线。 管芯附着区域包括一个或多个孔。 成型材料围绕引线框架结构的芯片附接区域和半导体管芯的至少一部分。 成型材料也在一个或多个孔内。

公开(公告)号：US20050051878A1

公开(公告)日：2005-03-10

申请号：US10660866

申请日：2003-09-11

Applicant: Honorio Granada ,  Rajeev Joshi ,  Connie Tangpuz

Inventor： Honorio Granada ,  Rajeev Joshi ,  Connie Tangpuz

IPC: H01L23/12 ,  H01L23/04 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L24/05 ,  H01L23/041 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.

Abstract translation: 一种芯片器件，包括具有管芯附接腔的引线框架。 存储装置还包括放置在管芯附着腔内的管芯。 管芯附着腔与模具基本上具有相同的厚度。 模具定位在腔内并且附接有标准模具附接程序。

公开(公告)号：US06806580B2

公开(公告)日：2004-10-19

申请号：US10330741

申请日：2002-12-26

Applicant: Rajeev Joshi ,  Maria Cristina B. Estacio

Inventor： Rajeev Joshi ,  Maria Cristina B. Estacio

IPC: H01L2348

CPC classification number: H05K1/141 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10689 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A multichip module is disclosed. In one embodiment, the multichip module includes a substrate having a first side and a second side, the first side being opposite to the first side. A driver chip is at the first side of the substrate. A semiconductor die comprising a vertical transistor is at the second side of the substrate. The driver chip and the semiconductor die are in electrical communication through the substrate.

Abstract translation: 公开了一种多芯片模块。 在一个实施例中，多芯片模块包括具有第一侧和第二侧的衬底，第一侧与第一侧相对。 驱动芯片位于基板的第一侧。 包括垂直晶体管的半导体管芯位于衬底的第二侧。 驱动器芯片和半导体管芯通过衬底电连通。

公开(公告)号：US06798044B2

公开(公告)日：2004-09-28

申请号：US09730932

申请日：2000-12-04

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L23495

CPC classification number: H01L24/12 ,  H01L23/3157 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A chip device including two stacked dies. The chip device includes a leadframe that includes a plurality of leads. A first die is coupled to a first side of the leadframe with solder and a second die is coupled to a second side of the leadframe with solder. A molded body surrounds at least a portion of the leadframe and the dies.

Abstract translation: 包括两个堆叠的芯片的芯片器件。 该芯片装置包括一个包括多个引线的引线框架。 第一裸片通过焊料耦合到引线框架的第一侧，并且第二裸片通过焊料耦合到引线框架的第二侧。 成型体围绕引线框架和模具的至少一部分。

公开(公告)号：US06753605B2

公开(公告)日：2004-06-22

申请号：US09731226

申请日：2000-12-04

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L2348

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/03831 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

Abstract translation: 用于制造芯片器件的凸起的晶片。 凸起的晶片包括在非钝化芯片上交替地与两个铜层溅射的两个钛层。 凸起的晶片在其上容纳的焊料凸起之下还包括凹凸材料。

公开(公告)号：US06731003B2

公开(公告)日：2004-05-04

申请号：US10386621

申请日：2003-03-11

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Erwin Victor R. Cruz

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Erwin Victor R. Cruz

IPC: H01L2348

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/45144 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01004

Abstract: A method for forming a semiconductor die package is disclosed. In one embodiment, the method includes forming a semiconductor die comprising a semiconductor device. A plurality of copper bumps is formed on the semiconductor die using a plating process. An adhesion layer is formed on each of the copper bumps, and a noble metal layer is formed on each of the copper bumps.

Abstract translation: 公开了一种用于形成半导体管芯封装的方法。 在一个实施例中，该方法包括形成包括半导体器件的半导体管芯。 使用电镀工艺在半导体管芯上形成多个铜凸块。 在每个铜凸块上形成粘合层，并且在每个铜凸块上形成贵金属层。

公开(公告)号：US06661082B1

公开(公告)日：2003-12-09

申请号：US09619115

申请日：2000-07-19

Applicant: Honorio T. Granada ,  Rajeev Joshi ,  Connie Tangpuz

Inventor： Honorio T. Granada ,  Rajeev Joshi ,  Connie Tangpuz

IPC: H01L23495

CPC classification number: H01L24/05 ,  H01L23/041 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.

Abstract translation: 一种芯片器件，包括具有管芯附接腔的引线框架。 存储装置还包括放置在管芯附着腔内的管芯。 管芯附着腔与模具基本上具有相同的厚度。 模具定位在腔内并且附接有标准模具附接程序。

公开(公告)号：US06294403B1

公开(公告)日：2001-09-25

申请号：US09522328

申请日：2000-03-09

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L2144

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. A silicon die is attached to a carrier (or substrate) that has a cavity substantially surrounding the die. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of the die as well as the edges of the carrier surrounding the die.

Abstract translation: 改进的半导体封装，将封装电阻降低到可忽略的水平，并提供出色的散热性能。 将硅片连接到具有基本上围绕裸片的空腔的载体（或基底）上。 然后通过分布在模具表面以及围绕模具的载体的边缘的焊料凸块的阵列制造硅片的有源表面与印刷电路板的直接连接。

公开(公告)号：US5765280A

公开(公告)日：1998-06-16

申请号：US788939

申请日：1997-01-24

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/34

CPC classification number: H01L24/97 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/403 ,  Y10T29/49144 ,  Y10T29/49789 ,  Y10T29/49799

Abstract: The present invention discloses the use of a dielectric substrate panel suitable for supporting a plurality of independently packaged ICs. The substrate panel has a plurality of conductive landings arranged on its top surface, a plurality of conductive contacts arranged on its bottom surface and a multiplicity of electrically conductive vias. The vias pass through the substrate panel and are arranged to interconnect selected landings with their associated conductive contacts. The top surface of the substrate panel also includes a number of die attach areas. During packaging, dies are secured to their associated die attach areas on the substrate panel and electrically coupled to appropriate conductive landings. An encapsulant is then formed over each of the dies for protection.

Abstract translation: 本发明公开了适用于支持多个独立封装的IC的电介质基板的使用。 衬底面板具有布置在其顶表面上的多个导电平台，布置在其底表面上的多个导电触头和多个导电通孔。 通孔穿过衬底面板并且布置成将选定的平台与其相关联的导电触点相互连接。 衬底面板的顶表面还包括多个管芯附接区域。 在包装期间，管芯被固定到其相关的管芯附着区域在基板面板上并且电耦合到适当的导电平台。 然后在每个模具上形成密封剂用于保护。

公开(公告)号：US08541890B2

公开(公告)日：2013-09-24

申请号：US11180367

申请日：2005-07-12

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.