公开(公告)号：US6097050A

公开(公告)日：2000-08-01

申请号：US282041

申请日：1999-03-30

申请人： Walter Hartner ,  Gunther Schindler ,  Carlos Mazure-Espejo

发明人： Walter Hartner ,  Gunther Schindler ,  Carlos Mazure-Espejo

IPC分类号： H01L25/18 ,  H01L21/60 ,  H01L25/00 ,  H01L25/04 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/72

CPC分类号： H01L27/11502 ,  H01L24/81 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/16237 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A memory configuration with a self-aligning non-integrated capacitor configuration includes a capacitor configuration and a transistor configuration which can be joined together in a self-aligning manner in such a way that each first contact of a transistor of the transistor configuration is connected to a respective second contact of a memory capacitor of the capacitor configuration. In order to align the two configurations, the second contacts are constructed in a protruding manner, and when joining takes place they engage in a structure including elevations.

摘要翻译： 具有自对准非集成电容器配置的存储器配置包括电容器配置和晶体管配置，其可以以自对准方式连接在一起，使得晶体管配置的晶体管的每个第一接触连接到 电容器配置的存储电容器的相应的第二接触。 为了对准这两种结构，第二触头以突出的方式构造，并且当接合发生时，它们接合包括高度的结构。

公开(公告)号：US6043529A

公开(公告)日：2000-03-28

申请号：US282099

申请日：1999-03-30

申请人： Walter Hartner ,  Gunther Schindler ,  Carlos Mazure-Espejo

发明人： Walter Hartner ,  Gunther Schindler ,  Carlos Mazure-Espejo

IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L29/78

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： The invention relates to a semiconductor configuration for integrated circuits, in which a stacked cell has a contact hole filled with a plug in an insulating layer, a capacitor having a lower electrode, which faces the plug, a paraelectric or ferroelectric dielectric and an upper electrode being provided on the contact hole. A barrier layer is situated between the plug and the lower electrode and is surrounded by a silicon nitride collar, which reliably prevents oxidation of the barrier layer.

摘要翻译： 本发明涉及一种用于集成电路的半导体结构，其中堆叠单元具有填充有绝缘层的插塞的接触孔，具有面向插塞的下电极的电容器，顺电或铁电电介质和上电极 设置在接触孔上。 阻挡层位于插塞和下电极之间，并且被氮化硅套环围绕，可靠地防止阻挡层的氧化。

公开(公告)号：US08669655B2

公开(公告)日：2014-03-11

申请号：US13564922

申请日：2012-08-02

申请人： Ottmar Geitner ,  Walter Hartner ,  Maciej Wojnowski ,  Ulrich Wachter ,  Michael Bauer ,  Andreas Stueckjuergen

发明人： Ottmar Geitner ,  Walter Hartner ,  Maciej Wojnowski ,  Ulrich Wachter ,  Michael Bauer ,  Andreas Stueckjuergen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/4763

CPC分类号： H01L24/96 ,  H01L23/3128 ,  H01L23/49855 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/24051 ,  H01L2224/32245 ,  H01L2224/73151 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/142 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/0103 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/13 ,  H01L2224/21 ,  H01L2924/00 ,  H01L2924/00014

摘要： A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.

摘要翻译： 提供了芯片封装，芯片封装包括：芯片，包括形成在芯片正面上的至少一个接触焊盘; 至少部分地围绕所述芯片并且覆盖所述至少一个接触垫的封装材料; 以及通过所述封装材料形成的至少一个电互连，其中所述至少一个电互连构造成将所述至少一个接触焊盘从所述芯片前侧的芯片封装第一侧电重定向至形成在所述芯片前侧的至少一个焊料结构 芯片封装第二面在芯片背面。

公开(公告)号：US20140035127A1

公开(公告)日：2014-02-06

申请号：US13563833

申请日：2012-08-01

申请人： Josef Hirtreiter ,  Walter Hartner ,  Ulrich Wachter ,  Juergen Foerster

发明人： Josef Hirtreiter ,  Walter Hartner ,  Ulrich Wachter ,  Juergen Foerster

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： H01L21/283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/13024 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/35121 ,  H01L2924/01015 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method for manufacturing a chip package is provided. The method includes: forming an electrically insulating material over a chip side; selectively removing at least part of the electrically insulating material thereby forming a trench in the electrically insulating material, depositing electrically conductive material in the trench wherein the electrically conductive material is electrically connected to at least one contact pad formed over the chip side; forming an electrically conductive structure over the electrically insulating material, wherein at least part of the electrically conductive structure is in direct physical and electrical connection with the electrically conductive material; and depositing a joining structure over the electrically conductive structure.

摘要翻译： 提供了一种制造芯片封装的方法。 该方法包括：在芯片侧上形成电绝缘材料; 选择性地去除所述电绝缘材料的至少一部分，从而在所述电绝缘材料中形成沟槽，在所述沟槽中沉积导电材料，其中所述导电材料电连接到在所述芯片侧上形成的至少一个接触焊盘; 在所述电绝缘材料上形成导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接; 以及在所述导电结构上沉积接合结构。

公开(公告)号：US07276300B2

公开(公告)日：2007-10-02

申请号：US10476579

申请日：2002-04-22

申请人： Zvonimir Gabric ,  Walter Hartner ,  Matthias Krönke ,  Günther Schindler

发明人： Zvonimir Gabric ,  Walter Hartner ,  Matthias Krönke ,  Günther Schindler

IPC分类号： B32B9/00

CPC分类号： H01L28/55 ,  H01L23/564 ,  H01L27/11502 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a microelectronic structure which provides improved protection of a hydrogen-sensitive dielectric against hydrogen contamination. According to the invention, the hydrogen sensitive dielectric (14) is covered at lest by an intermediate oxide (18), where material thickness is at lest five times the thickness of the hydrogen-sensitive dielectric. The intermediate oxide (18) simultaneously acts as an internal dielectric and is metabolized on its surface for this purpose. The intermediate oxide (18), which has a sufficient thickness absorbers the hydrogen that may be released during the deposition of a hydrogen barrier layer (22, 26), thus protecting the hydrogen-sensitive dielectric (14).

摘要翻译： 本发明涉及一种微电子结构，其提供对氢敏感介质的改善的防止氢污染的保护。 根据本发明，氢敏电介质（14）几乎被中间氧化物（18）覆盖，其中材料厚度是氢敏电介质厚度的五倍。 中间氧化物（18）同时作为内部电介质，为此目的在其表面上代谢。 具有足够厚度的中间氧化物（18）吸收在氢阻挡层（22,26）的沉积过程中可释放的氢，从而保护感应电介质（14）。

公开(公告)号：US20060160324A1

公开(公告)日：2006-07-20

申请号：US11036536

申请日：2005-01-14

申请人： Walter Hartner ,  Joseph Page ,  Jonathan Davis

发明人： Walter Hartner ,  Joseph Page ,  Jonathan Davis

IPC分类号： H01L21/461

CPC分类号： H01L21/31055

摘要： A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the spin processing unit to direct the etching solution along a radius of the wafer; adjusting the flow of the etching solution from the nozzle; adjusting the rotational speed of the spin susceptor to control the residence time of the etching solution; and coordinating the rotational speed of the spin susceptor, flow of etching solution and positioning of the nozzle to maximize the removal of material. The process may be utilized to compensate for the bowl-shaped non-uniformities of an STI oxide. These non-uniformities are compensated for and addressed after a CMP process.

摘要翻译： 一种用于补偿晶片上的径向不均匀性的方法和方法，包括以下步骤：在CMP工艺之后使膜周围的旋转基座的轴线上的膜的旋转厚度不均匀性居中; 将喷嘴定位在旋转处理单元中以沿着晶片的半径引导蚀刻溶液; 从喷嘴调节蚀刻溶液的流动; 调整旋转基座的旋转速度以控制蚀刻溶液的停留时间; 并协调旋转基座的旋转速度，蚀刻溶液的流动和喷嘴的定位，以最大限度地去除材料。 该方法可用于补偿STI氧化物的碗形不均匀性。 这些非均匀性在CMP过程之后得到补偿和解决。

公开(公告)号：US06825116B2

公开(公告)日：2004-11-30

申请号：US09845405

申请日：2001-04-30

申请人： Gerhard Beitel ,  Mattias Ahlstedt ,  Walter Hartner ,  Günther Schindler ,  Marcus Kastner ,  Volker Weinrich

发明人： Gerhard Beitel ,  Mattias Ahlstedt ,  Walter Hartner ,  Günther Schindler ,  Marcus Kastner ,  Volker Weinrich

IPC分类号： H01L21302

CPC分类号： H01L28/55 ,  H01L21/31053 ,  H01L21/3212 ,  H01L27/10811 ,  H01L27/11507

摘要： A method for removing structures from a substrate is described. The method includes providing a substrate that has the structures that must be removed, applying a sacrifice layer, and removing the structures and the sacrifice layer in a polishing step. The method has the advantage that the sacrifice layer surrounds the structures that must be removed and stabilizes them, so that the structures can be eroded slowly and successively in the subsequent polishing step without breaking off. This prevents a smearing of the material of the structures such as occurs given direct polishing without a sacrifice layer.

摘要翻译： 描述了从衬底去除结构的方法。 该方法包括提供具有必须去除的结构的基底，施加牺牲层，以及在抛光步骤中去除结构和牺牲层。 该方法的优点在于，牺牲层围绕必须被去除和稳定的结构，从而可以在随后的抛光步骤中缓慢且连续地腐蚀结构而不会断裂。 这样可以防止结构材料的污染，例如直接抛光而没有牺牲层。

公开(公告)号：US06790676B2

公开(公告)日：2004-09-14

申请号：US10204830

申请日：2002-12-05

申请人： Hans Cerva ,  Walter Hartner ,  Frank Hintermaier ,  Joachim Hoepfner ,  Guenther Schindler ,  Volker Weinrich ,  Franz Winterauer

发明人： Hans Cerva ,  Walter Hartner ,  Frank Hintermaier ,  Joachim Hoepfner ,  Guenther Schindler ,  Volker Weinrich ,  Franz Winterauer

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L21/31691 ,  H01L27/11507 ,  H01L28/55

摘要： A method for producing a ferroelectric layer includes preparing a substrate, applying a layer of material, which will be subsequently converted into the ferroelectric layer, and changing the material into the ferroelectric layer by applying an outer electrical field aligned with the direction desired in the ferroelectric material and heat treating the material. By providing a first noble metal electrode on the surface before applying the material that is to become the ferroelectric layer and then subsequently forming a second noble metal electrode on the ferroelectric layer, a ferroelectric storage capacitor can be formed. If the substrate is provided with memory cells, which include at least one transistor for each cell and the above-mentioned ferroelectric storage capacitors, a ferroelectric memory arrangement can be produced.

摘要翻译： 一种铁电体层的制造方法，其特征在于，准备基板，涂敷随后转变为铁电体层的材料层，并且通过施加与铁电体中所需的方向对准的外部电场，将材料变更为铁电体层 材料和热处理材料。 通过在施加成为铁电体层的材料之后，在表面上设置第一贵金属电极，然后在铁电体层上形成第二贵金属电极，可以形成铁电存储电容器。 如果衬底设置有存储单元，其包括用于每个单元的至少一个晶体管和上述铁电存储电容器，则可以制造铁电存储器布置。

公开(公告)号：US06656787B2

公开(公告)日：2003-12-02

申请号：US09962694

申请日：2001-09-24

申请人： Günther Schindler ,  Walter Hartner

发明人： Günther Schindler ,  Walter Hartner

IPC分类号： H01L218242

CPC分类号： H01L27/11502 ,  H01L21/31122 ,  H01L21/32136 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： A method for fabricating a semiconductor component includes the steps of applying an electrode material and a metal-oxide-containing layer on a substrate surface and selectively etching the electrode material and the metal-oxide-containing layer for forming a first electrode from the electrode material and forming a metal oxide layer from the metal-oxide-containing layer, wherein the metal oxide layer is disposed on top of the first electrode. The method further includes conformally applying a conductive material which has a given material thickness, anisotropically etching the conductive material for fabricating a resistance element in the form of a self-aligned lateral edge web on at least one sidewall of the metal oxide layer and of the first electrode, and applying a further electrode material at least on the resistance element for forming a second electrode.

摘要翻译： 一种制造半导体部件的方法包括以下步骤：在基板表面上施加电极材料和含金属氧化物的层，并从电极材料选择性地蚀刻用于形成第一电极的电极材料和含金属氧化物的层 以及从所述含金属氧化物的层形成金属氧化物层，其中所述金属氧化物层设置在所述第一电极的顶部。 该方法还包括共形施加具有给定材料厚度的导电材料，各向异性地蚀刻导电材料，以在金属氧化物层的至少一个侧壁上制造自对准侧边缘纤维网形式的电阻元件，以及 第一电极，并且至少在用于形成第二电极的电阻元件上施加另外的电极材料。

公开(公告)号：US06649468B2

公开(公告)日：2003-11-18

申请号：US09939249

申请日：2001-08-24

申请人： Günther Schindler ,  Zvonimir Gabric ,  Walter Hartner

发明人： Günther Schindler ,  Zvonimir Gabric ,  Walter Hartner

IPC分类号： H01L218242

CPC分类号： H01L28/55 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76841

摘要： A method for fabricating a microelectronic component includes the step of applying a barrier against the passage of hydrogen to a storage capacitor having a ferroelectric dielectric or a paraelectric dielectric. During the formation of the barrier, firstly a silicon oxide layer is produced, the latter is then subjected to a heat treatment and a barrier layer is subsequently applied. A microelectronic component has a storage capacitor and a barrier including a silicon oxide layer and a barrier layer. The silicon oxide layer is disposed on an electrode of the storage capacitor and has been subjected to a heat treatment in an oxygen-containing atmosphere. The barrier layer is disposed on the silicon oxide layer and protects the storage capacitor against a passage of hydrogen through the barrier.

摘要翻译： 微电子部件的制造方法包括：将阻止氢气通过的阻挡层施加于具有铁电电介质或顺电介质的储能电容器的工序。 在形成屏障期间，首先制造氧化硅层，然后对其进行热处理，随后施加阻挡层。 微电子部件具有存储电容器和包括氧化硅层和阻挡层的阻挡层。 氧化硅层设置在储存电容器的电极上，并且在含氧气氛中进行热处理。 阻挡层设置在氧化硅层上，并保护储存电容器免受通过屏障的氢气通道。