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    METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVCIE HAVING CAPACITOR ELEMENT
    33.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVCIE HAVING CAPACITOR ELEMENT 审中-公开
    具有电容元件的半导体集成电路制造方法

    公开(公告)号：US20110012181A1

    公开(公告)日：2011-01-20

    申请号：US12890431

    申请日：2010-09-24

    申请人： Naotaka HASHIMOTO ,  Yutaka Hoshino ,  Shuji Ikeda

    发明人： Naotaka HASHIMOTO ,  Yutaka Hoshino ,  Shuji Ikeda

    IPC分类号： H01L27/108 ,  H01L27/092 ,  H01L21/8238

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

    摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

    摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

    Methods for Fabricating Semiconductor Structures
    36.
    发明申请
    Methods for Fabricating Semiconductor Structures 有权
    制造半导体结构的方法

    公开(公告)号：US20080176406A1

    公开(公告)日：2008-07-24

    申请号：US11625585

    申请日：2007-01-22

    申请人： Shuji Ikeda ,  Jeff Wetzel ,  James Beach ,  Charles Stager ,  Michael Gotskowski ,  Andrew Collin Campbell

    发明人： Shuji Ikeda ,  Jeff Wetzel ,  James Beach ,  Charles Stager ,  Michael Gotskowski ,  Andrew Collin Campbell

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/1037 ,  H01L29/78

    摘要： Methods for fabricating semiconductor structures are provided. A first layer may be deposited onto a substrate followed by the deposition of a second layer onto the first layer. A plurality of line structures may be etched in the second layer. A third layer, deposited onto the plurality of line structures of the second layer, may subsequently be etched to expose the plurality of line structures in the second layer. The plurality of line structures in the second layer may be removed, leaving an etched third layer. The etched third layer may be used as a mask to etch the first layer to form a semiconductor structure in the first layer. In some respects, the methods may include steps for etching the substrate using the etched first layer. The methods may also provide annealing the etched substrate to form a corrugate substrate surface.

    摘要翻译： 提供制造半导体结构的方法。 可以将第一层沉积在基底上，随后将第二层沉积到第一层上。 可以在第二层中蚀刻多个线结构。 沉积在第二层的多个线结构上的第三层可随后被蚀刻以露出第二层中的多个线结构。 可以去除第二层中的多个线结构，留下蚀刻的第三层。 蚀刻的第三层可以用作掩模以蚀刻第一层以在第一层中形成半导体结构。 在某些方面，该方法可以包括使用蚀刻的第一层蚀刻衬底的步骤。 该方法还可以提供对蚀刻的衬底进行退火以形成波纹衬底表面。

    Semiconductor Device
    37.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20080061384A1

    公开(公告)日：2008-03-13

    申请号：US11936443

    申请日：2007-11-07

    申请人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

    发明人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823462 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/823412 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78696

    摘要： Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

    摘要翻译： 在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅电介质膜6,7和栅电极8，以便成为MOS晶体管。 氧化锆或氧化铪被用作栅极电介质膜6,7的主要成分。例如通过CVD形成栅极绝缘膜6,7。 作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。在使用其表面为（111）的基板的情况下， 在使用表面为（001）晶面的硅衬底的情况下，氧的扩散系数小于氧的扩散系数的1/100，并且控制氧扩散。 因此，控制氧扩散，防止漏电流的产生，提高性能。 实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

    Semiconductor device and manufacturing method of the same
    38.
    发明授权
    Semiconductor device and manufacturing method of the same 失效
    半导体器件及其制造方法相同

    公开(公告)号：US07084477B2

    公开(公告)日：2006-08-01

    申请号：US10600771

    申请日：2003-06-23

    申请人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

    发明人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11526 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546

    摘要： To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

    摘要翻译： 为了抑制在半导体衬底中发生的缺陷，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面 定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

    Semiconductor integrated circuit device
    40.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20050146961A1

    公开(公告)日：2005-07-07

    申请号：US11042172

    申请日：2005-01-26

    申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC分类号： H01L27/10 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/02

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    摘要翻译： 现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致 不对称性导致了微图案化困难的问题的发生。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分为两部分，它们设置在N型阱区NW 1的相对侧，并形成为 形成晶体管的扩散层没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。