公开(公告)号：US10410864B2

公开(公告)日：2019-09-10

申请号：US15988830

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan Kwon ,  Rui Cheng ,  Abhijit Basu Mallick ,  Er-Xuan Ping ,  Jaesoo Ahn

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L27/11582 ,  H01L49/02

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

公开(公告)号：US20190172723A1

公开(公告)日：2019-06-06

申请号：US15951637

申请日：2018-04-12

Applicant: Applied Materials, Inc.

Inventor： Rui Cheng ,  Abhijit Basu Mallick ,  Pramit Manna ,  Yihong Chen

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/311

Abstract: Methods for seam-less gapfill comprising depositing a film in a feature, treating the film to change some film property and selectively etching the film from the top surface are described. The deposition, treatment and etching are repeated to form a seam-less gapfill in the feature.

公开(公告)号：US09624577B2

公开(公告)日：2017-04-18

申请号：US14697385

申请日：2015-04-27

Applicant: Applied Materials, Inc.

Inventor： Pramit Manna ,  Abhijit Basu Mallick ,  Mukund Srinivasan ,  Rui Cheng

IPC: C23F1/02 ,  C23C16/26 ,  C23C16/04 ,  C23C16/06 ,  H01J37/32 ,  C23C16/30

CPC classification number: C23C16/26 ,  C23C16/042 ,  C23C16/06 ,  C23C16/30 ,  H01J37/32091

Abstract: Embodiments of the present disclosure relate to a metal-doped amorphous carbon hardmask for etching the underlying layer, layer stack, or structure. In one embodiment, a method of processing a substrate in a processing chamber includes exposing a substrate to a gas mixture comprising a carbon-containing precursor and a metal-containing precursor, reacting the carbon-containing precursor and the metal-containing precursor in the processing chamber to form a metal-doped carbon layer over a surface of the substrate, forming in the metal-doped carbon layer a defined pattern of through openings, and transferring the defined pattern to an underlying layer beneath the metal-doped carbon layer using the metal-doped carbon layer as a mask. An etch hardmask using the inventive metal-doped amorphous carbon film provides reduced compressive stress, high hardness, and therefore higher etch selectivity.

公开(公告)号：US12062567B2

公开(公告)日：2024-08-13

申请号：US16844764

申请日：2020-04-09

Applicant: Applied Materials, Inc.

Inventor： Zubin Huang ,  Rui Cheng ,  Diwakar Kedlaya ,  Satish Radhakrishnan ,  Anton V. Baryshnikov ,  Venkatanarayana Shankaramurthy ,  Karthik Janakiraman ,  Paul L. Brillhart ,  Badri N. Ramamurthi

IPC: H01L21/683 ,  H01J37/32 ,  H01L21/67

CPC classification number: H01L21/6838 ,  H01J37/32724 ,  H01L21/67017 ,  H01L21/67167 ,  H01L21/67253 ,  H01J2237/186 ,  H01J2237/24585

Abstract: Exemplary methods of semiconductor processing may include coupling a fluid conduit within a substrate support in a semiconductor processing chamber to a system foreline. The coupling may vacuum chuck a substrate with the substrate support. The methods may include flowing a gas into the fluid conduit. The methods may include maintaining a pressure between the substrate and the substrate support at a pressure higher than the pressure at the system foreline.

公开(公告)号：US11981998B2

公开(公告)日：2024-05-14

申请号：US17085255

申请日：2020-10-30

Applicant: Applied Materials, Inc.

Inventor： Zubin Huang ,  Rui Cheng ,  Jian Li

IPC: C23C16/46 ,  C23C16/455 ,  C23C16/458 ,  H01J37/32

CPC classification number: C23C16/466 ,  C23C16/45563 ,  C23C16/4581 ,  H01J37/32724

Abstract: Exemplary temperature modulation methods may include delivering a gas through a purge line extending within a substrate support. The gas may be directed to a backside surface of the substrate support opposite a substrate support surface. The purge line may extend along a central axis of a shaft, the shaft being hermetically sealed with the substrate support. The substrate support may be characterized by a center and a circumferential edge. A first end of the purge line may be fixed at a first distance from the backside surface of the substrate support. The methods may include flowing the gas at a first flow rate via a flow pathway to remove heat from the substrate support to achieve a desired substrate support temperature profile.

公开(公告)号：US11961739B2

公开(公告)日：2024-04-16

申请号：US17063339

申请日：2020-10-05

Applicant: Applied Materials, Inc.

Inventor： Yi Yang ,  Krishna Nittala ,  Rui Cheng ,  Karthik Janakiraman ,  Diwakar Kedlaya ,  Zubin Huang ,  Aykut Aydin

IPC: H01L21/033 ,  C23C16/38

CPC classification number: H01L21/0337 ,  C23C16/38 ,  H01L21/0332

Abstract: Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H2) into the substrate processing region of the semiconductor processing chamber. The boron-containing precursor and the H2 may be flowed at a boron-to-hydrogen flow rate ratio. The flow rate of the boron-containing precursor and the H2 may be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. The boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.

公开(公告)号：US11830706B2

公开(公告)日：2023-11-28

申请号：US16703140

申请日：2019-12-04

Applicant: Applied Materials, Inc.

Inventor： Venkata Sharat Chandra Parimi ,  Zubin Huang ,  Jian Li ,  Satish Radhakrishnan ,  Rui Cheng ,  Diwakar N. Kedlaya ,  Juan Carlos Rocha-Alvarez ,  Umesh M. Kelkar ,  Karthik Janakiraman ,  Sarah Michelle Bobek ,  Prashant Kumar Kulshreshtha ,  Vinay K. Prabhakar ,  Byung Seok Kwon

IPC: H01L21/67 ,  H05B3/10 ,  H01J37/32 ,  C23C16/458 ,  C23C16/50 ,  C23C16/46 ,  H05B3/14

CPC classification number: H01J37/32724 ,  C23C16/4583 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/50 ,  H01J37/32715 ,  H01L21/67103 ,  H05B3/10 ,  H05B3/143 ,  H01J2237/2007 ,  H01J2237/3321

Abstract: Embodiments of the present disclosure generally relate to a pedestal for increasing temperature uniformity in a substrate supported thereon. The pedestal comprises a body having a heater embedded therein. The body comprises a patterned surface that includes a first region having a first plurality of posts extending from a base surface of the body at a first height, and a second region surrounding the central region having a second plurality of posts extending from the base surface at a second height that is greater than the first height, wherein an upper surface of each of the first plurality of posts and the second plurality of posts are substantially coplanar and define a substrate receiving surface.

公开(公告)号：US20230309300A1

公开(公告)日：2023-09-28

申请号：US17705135

申请日：2022-03-25

Applicant: Applied Materials, Inc.

Inventor： Dimitrios Pavlopoulos ,  Rui Cheng ,  Qinghua Zhao ,  Karthik Janakiraman

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L21/02208

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. Alternating layers of material may be formed on the substrate. One or more recesses may be formed in the alternating layers of material. The methods may include forming a first silicon-containing material. The first silicon-containing material may extend into the one or more recesses formed in the alternating layers of material. The methods may include providing a halogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a silicon-and-halogen-containing material. The silicon-and-halogen-containing material may overly the first silicon-containing material. The methods may include forming a second silicon-containing material. The second silicon-containing material may overly the silicon-and-halogen-containing material.

公开(公告)号：US11769666B2

公开(公告)日：2023-09-26

申请号：US17379508

申请日：2021-07-19

Applicant: Applied Materials, Inc.

Inventor： Rui Cheng ,  Fei Wang ,  Abhijit Basu Mallick ,  Robert Jan Visser

IPC: H01L21/02 ,  A61K9/00 ,  A61K31/438 ,  A61K31/4409 ,  A61K31/47 ,  A61K31/497 ,  A61K47/12 ,  A61K47/26 ,  A61K47/36 ,  H01L21/3065

CPC classification number: H01L21/02636 ,  A61K9/0024 ,  A61K31/438 ,  A61K31/4409 ,  A61K31/47 ,  A61K31/497 ,  A61K47/12 ,  A61K47/26 ,  A61K47/36 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02664 ,  H01L21/3065

Abstract: Methods for selective silicon film deposition on a substrate comprising a first surface and a second surface are described. More specifically, the process of depositing a film, treating the film to change some film property and selectively etching the film from various surfaces of the substrate are described. The deposition, treatment and etching can be repeated to selectively deposit a film on one of the two substrate surfaces.

公开(公告)号：US11676813B2

公开(公告)日：2023-06-13

申请号：US17025009

申请日：2020-09-18

Applicant: Applied Materials, Inc.

Inventor： Aykut Aydin ,  Rui Cheng ,  Yi Yang ,  Krishna Nittala ,  Karthik Janakiraman ,  Bo Qi ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  H01L21/324 ,  H01J37/32 ,  C23C16/56 ,  C23C16/50 ,  C23C16/30 ,  C23C16/24

CPC classification number: H01L21/0257 ,  C23C16/24 ,  C23C16/30 ,  C23C16/50 ,  C23C16/56 ,  H01J37/3244 ,  H01L21/02532 ,  H01L21/324 ,  H01J2237/332

Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the silicon-containing precursor and the boron-containing precursor. The dopant-containing precursor may include one or more of carbon, nitrogen, oxygen, or sulfur. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The silicon-and-boron material may include greater than or about 1 at. % of a dopant from the dopant-containing precursor.