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    Semiconductor integrated circuit having logi gates
    32.
    发明授权
    Semiconductor integrated circuit having logi gates 失效
    具有逻辑门的半导体集成电路

    公开(公告)号：US5675548A

    公开(公告)日：1997-10-07

    申请号：US608605

    申请日：1996-02-29

    申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

    CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

    摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

    摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种用于这种半导体存储器电路的改进的读/写布置，该电路包括用于在写入操作期间公共读取线与数据线的连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

    SEMICONDUCTOR DEVICE
    33.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150098289A1

    公开(公告)日：2015-04-09

    申请号：US14508744

    申请日：2014-10-07

    申请人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

    发明人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

    IPC分类号： G11C11/406

    CPC分类号： G11C11/40615 ,  G11C11/40603 ,  G11C16/26

    摘要： A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

    摘要翻译： 半导体器件包括多个存储器单元，存取电路，被配置为对存储器单元执行数据读取操作，数据写入操作和数据刷新操作，所述存取电路以选择的第一模式操作 准备执行的第二模式和未准备好执行的第二模式;以及判断电路，被配置为响应于第一命令信息，以使得当访问电路处于第一模式时，访问电路执行数据刷新操作，以及 当访问电路处于第二模式时，访问电路从第二模式退出，然后执行刷新操作。

    Semiconductor package
    36.
    发明申请
    Semiconductor package 审中-公开
    半导体封装

    公开(公告)号：US20090001548A1

    公开(公告)日：2009-01-01

    申请号：US12213559

    申请日：2008-06-20

    申请人： Fumiyuki Osanai ,  Toshio Sugano ,  Atsushi Hiraishi

    发明人： Fumiyuki Osanai ,  Toshio Sugano ,  Atsushi Hiraishi

    IPC分类号： H01L23/48

    CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/3011

    摘要： A semiconductor package which includes: a semiconductor chip which includes a signal terminal for inputting and outputting electrical signals and a ground terminal; and a package substrate which includes a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a terminal electrode forming surface on which a signal terminal electrode electrically connected to the signal terminal and a ground terminal electrode electrically connected to the ground terminal are arranged in an array pattern, wherein: on the semiconductor chip mounting surface, there is provided a first signal wiring connected to the signal terminal, a ground wiring connected to the ground terminal, and a ground conductive layer connected to the ground wiring and is provided in a planar pattern in an area excluding the forming area of the first signal wiring; on the terminal electrode forming surface, there is provided a second signal wiring connected to the signal terminal electrode, and a ground fine wiring connected to the ground terminal electrode; and the first signal wiring and the second signal wiring are connected via a conductor filled in a signal through hole penetrating the package substrate, and the ground conductive layer and the ground fine wiring are connected via a conductor filled in a ground through hole penetrating the package substrate.

    摘要翻译： 一种半导体封装件，包括：半导体芯片，其包括用于输入和输出电信号的信号端子和接地端子; 以及包括其上安装有半导体芯片的半导体芯片安装面的封装基板以及与该信号端子电连接的信号端子电极和与接地端子电连接的接地端子电极的端子电极形成面 在阵列图案中，其中：在半导体芯片安装表面上，提供连接到信号端子的第一信号布线，连接到接地端子的接地布线和连接到接地布线的接地导电层，并且设置在 在除了第一信号布线的形成区域之外的区域中的平面图案; 在端子电极形成表面上设置连接到信号端子电极的第二信号布线和连接到接地端子电极的接地精细布线; 并且第一信号布线和第二信号布线经由填充在穿过封装基板的信号通孔中的导体连接，并且接地导体层和接地精细布线经由填充在地面中的导体穿过穿过封装的孔而连接 基质。

    Memory module
    37.
    发明授权
    Memory module 有权
    内存模块

    公开(公告)号：US07440289B2

    公开(公告)日：2008-10-21

    申请号：US11987080

    申请日：2007-11-27

    申请人： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    发明人： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    IPC分类号： H05K7/00

    CPC分类号： H05K1/181 ,  G11C5/00 ,  H05K1/0298 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611

    摘要： A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.

    摘要翻译： 存储器模块包括经由模块基板设置在与存储器缓冲器相对的位置处的存储器芯片MC1，经由模块基板设置在与存储器缓冲器不相对的位置处的存储芯片MC 3和布置在存储器缓冲器 在与存储芯片MC3相对的位置经由模块基板。 连接到存储芯片MC 1的布线部分和连接到存储芯片MC 3和MC 11的布线部分分支的分支点位于从平面安装位置 的存储器缓冲器和存储芯片MC 3和MC 11的平面安装位置。 因此，可以使布线部的布线长度足够短。

    Semiconductor integrated circuit device and process for fabricating the same
    39.
    发明授权
    Semiconductor integrated circuit device and process for fabricating the same 失效
    半导体集成电路器件及其制造方法

    公开(公告)号：US5767554A

    公开(公告)日：1998-06-16

    申请号：US460639

    申请日：1995-06-02

    申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

    发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

    IPC分类号： H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

    摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。