公开(公告)号：US5696018A

公开(公告)日：1997-12-09

申请号：US487197

申请日：1995-06-07

申请人： Scott R. Summerfelt ,  Jason Reid ,  Marc Nicolet ,  Elzbieta Kolawa

发明人： Scott R. Summerfelt ,  Jason Reid ,  Marc Nicolet ,  Elzbieta Kolawa

IPC分类号： H01G4/33 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/92 ,  H01L21/28

CPC分类号： H01L28/60 ,  H01L28/55 ,  H01L28/75

摘要： A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

公开(公告)号：US5626773A

公开(公告)日：1997-05-06

申请号：US367659

申请日：1995-01-03

申请人： James F. Belcher ,  Howard R. Beratan ,  Scott R. Summerfelt

发明人： James F. Belcher ,  Howard R. Beratan ,  Scott R. Summerfelt

IPC分类号： G01J1/02 ,  G01J5/34 ,  H01L21/302 ,  H01L21/3065 ,  H01L27/14 ,  H01L37/02 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06 ,  C23F1/00

CPC分类号： H01L37/02 ,  G01J5/34 ,  Y10S438/942

摘要： An array of thermal sensor elements (16) is formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of metal contacts (60) is formed to define masked (61) and unmasked (68) regions of the substrate (46). A second layer of metal contacts (62) is formed on the first layer of contacts (60). A radiation etch mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). A dry-etch mask layer (74) is formed to encapsulate the exposed portions of the first layer of contacts (60) and radiation etch mask layer (66). An initial portion of each unmasked region (68) is etched using a dry-etch process. The remaining portions of the unmasked regions (68) are exposed to an etchant (70) and irradiated with electromagnetic energy to substantially increase the reactivity between the remaining portions and the etchant (70). During such irradiation, the etchant (70) etches the remaining portions substantially faster than the first layer of contacts (60) and the radiation etch mask layer (66).

公开(公告)号：US5619393A

公开(公告)日：1997-04-08

申请号：US472149

申请日：1995-06-07

申请人： Scott R. Summerfelt ,  Howard R. Beratan ,  Bruce E. Gnade

发明人： Scott R. Summerfelt ,  Howard R. Beratan ,  Bruce E. Gnade

IPC分类号： H01L21/02 ,  H01G4/005

CPC分类号： H01L28/55 ,  H01L28/60 ,  Y10T29/435

摘要： A preferred embodiment of this invention comprises a thin unreactive film (e.g. ruthenium dioxide 36) contacting a high-dielectric-constant material (e.g. barium strontium titanate 38) to an electrode. The thin unreactive film provides a stable conductive interface between the high-dielectric-constant material layer and the electrode base (e.g palladium 34). As opposed to a standard thin-film layer, the thin unreactive film is generally less than 50 nm thick, preferably less than 35 nm thick, more preferably between 5 nm and 25 nm thick, and most preferably between 10 nm and 20 nm thick. A thin unreactive film can benefit from the advantages of the materials used while avoiding or minimizing many of their disadvantages. A thin unreactive film would generally be substantially less expensive than a standard thin-film layer since much less material can be used while not significantly affecting the surface area of the electrode in contact with the HDC material. These structures may also be used for multilayer capacitors and other thin-film ferroelectric devices such as pyroelectric materials, non-volatile memories, thin-film piezoelectric and thin-film electro-optic oxides.

摘要翻译： 本发明的优选实施方案包括使高介电常数材料（例如钛酸钡锶38）与电极接触的薄的非反应性膜（例如二氧化钌36）。 薄的非反应性膜在高介电常数材料层和电极基底（例如钯34）之间提供稳定的导电界面。 与标准薄膜层相反，薄的非反应性膜通常小于50nm厚，优选小于35nm厚，更优选在5nm和25nm之间，最优选在10nm和20nm之间。 薄的非反应性膜可以受益于所使用的材料的优点，同时避免或最小化许多它们的缺点。 薄的非反应性膜通常比标准薄膜层便宜得多，因为可以使用更少的材料，而不会显着影响与HDC材料接触的电极的表面积。 这些结构也可以用于多层电容器和其他薄膜铁电体器件，例如热电材料，非易失性存储器，薄膜压电和薄膜电光氧化物。

公开(公告)号：US5609927A

公开(公告)日：1997-03-11

申请号：US476950

申请日：1995-06-06

申请人： Scott R. Summerfelt ,  Howard R. Beratan ,  Robert Tsu

发明人： Scott R. Summerfelt ,  Howard R. Beratan ,  Robert Tsu

IPC分类号： H01L27/04 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/314 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  B05D3/06

CPC分类号： H01L21/3105 ,  H01L21/31122

摘要： Processing techniques for processing high-dielectric-constant material are provided to allow for the formation of an electronic device (10) which comprises a inner electrode (24), a high-dielectric-constant layer (28), and an outer electrode (30). High-dielectric-constant layer (28) is subjected to ultraviolet radiation in an oxygen ozone ambient to eliminate various undesirable hydroxide and carbonate compounds. Layer (28) is further subjected to high pressure isotropic reactive ion etches prior to the deposition of layer (30). The interface between layer (28) and layer (30) is exposed to reactive fluorine and low pressure plasma to improve the fair electric properties and leakage currents associated with layer (28).

摘要翻译： 提供了用于处理高介电常数材料的处理技术，以便形成电子器件（10），该电子器件包括内部电极（24），高介电常数层（28）和外部电极（30） ）。 高介电常数层（28）在氧气臭氧环境中进行紫外线辐射以消除各种不希望的氢氧化物和碳酸盐化合物。 层（28）在沉积层（30）之前进一步经受高压各向同性反应离子蚀刻。 层（28）和层（30）之间的界面暴露于反应性氟和低压等离子体以改善与层（28）相关联的公平的电性能和泄漏电流。

公开(公告)号：US5589284A

公开(公告)日：1996-12-31

申请号：US474803

申请日：1995-06-07

申请人： Scott R. Summerfelt ,  Howard R. Beratan

发明人： Scott R. Summerfelt ,  Howard R. Beratan

IPC分类号： B32B18/00 ,  C04B35/01 ,  C04B35/50

CPC分类号： C04B35/01 ,  C04B35/50

摘要： A preferred embodiment of this invention comprises a perovskite-seed layer (e.g. calcium ruthenate 40) between a conductive oxide layer (e.g. ruthenium oxide 36) and a perovskite dielectric material (e.g. barium strontium titanate 42), wherein the perovskite-seed layer and the conductive oxide layer each comprise the same metal. The metal should be conductive in its metallic state and should remain conductive when partially or fully oxidized. Generally, the perovskite-seed layer has a perovskite or perovskite-like crystal structure and lattice parameters which are similar to the perovskite dielectric layer formed thereon. At a given deposition temperature, the crystal quality and other properties of the perovskite dielectric will generally be enhanced by depositing it on a surface having a similar crystal structure. Undesirable crystal structure formation will generally be minimized and lower processing temperatures may be used to deposit the perovskite dielectric layer. Another benefit of this electrode system is that the perovskite-seed layer should do little or no reduction of the perovskite dielectric layer.

摘要翻译： 本发明的优选实施方案包括在导电氧化物层（例如氧化钌36）和钙钛矿电介质材料（例如钛酸钡锶42）之间的钙钛矿种子层（例如，钌酸钙40），其中钙钛矿种子层和 导电氧化物层各自包含相同的金属。 金属应在金属状态下导电，并且当部分或完全氧化时应保持导电性。 通常，钙钛矿种子层具有类似于其上形成的钙钛矿电介质层的钙钛矿或钙钛矿型晶体结构和晶格参数。 在给定的沉积温度下，钙钛矿电介质的晶体质量和其它性质通常会通过将其沉积在具有类似晶体结构的表面上来增强。 通常将不期望的晶体结构形成最小化，并且可以使用较低的加工温度来沉积钙钛矿电介质层。 该电极系统的另一个优点是钙钛矿种子层应该很少或不会减少钙钛矿电介质层。

公开(公告)号：US5520992A

公开(公告)日：1996-05-28

申请号：US81484

申请日：1993-06-22

申请人： Monte A. Douglas ,  Scott R. Summerfelt

发明人： Monte A. Douglas ,  Scott R. Summerfelt

IPC分类号： H01B1/06 ,  H01G4/008 ,  H01G4/012 ,  H01G4/10 ,  H01G4/232 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  C23C14/06

CPC分类号： H01G4/008 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/55 ,  H01L28/65 ,  Y10T428/24917

摘要： Novel methods of forming capacitors containing high dielectric materials are disclosed. Capacitors are made by forming a layer of conductive metal nitride (e.g. ruthenium nitride, 28), then forming a layer of a high dielectric constant material (e.g. barium strontium titanate, 30) on the metal nitride layer, then forming a layer of a non-metal containing electrically conductive compound (e.g. ruthenium oxide, 32) on the layer of high dielectric constant material. Typically, the high dielectric constant material is a transition metal oxide, a titanate, a titanate doped with one or more rare earth elements, a titanate doped with one or more alkaline earth metals, or combinations thereof. Preferably, the conductive compound is ruthenium nitride, ruthenium dioxide, tin nitride, tin oxide, titanium nitride, titanium monoxide, or combinations thereof. The conductive compound may be doped to increase its electrical conductivity.

摘要翻译： 公开了形成含有高介电材料的电容器的新方法。 电容器通过形成一层导电金属氮化物（例如，氮化钌28），然后在金属氮化物层上形成一层高介电常数材料（例如钛酸钡锶30），然后形成一层非金属 在高介电常数材料层上含有导电化合物（例如氧化钌32）的金属。 通常，高介电常数材料是过渡金属氧化物，钛酸盐，掺杂有一种或多种稀土元素的钛酸盐，掺杂有一种或多种碱土金属的钛酸盐或其组合。 优选地，导电化合物是氮化钌，二氧化钌，氮化锡，氧化锡，氮化钛，一氧化钛或其组合。 可以掺杂导电化合物以增加其导电性。

公开(公告)号：US5489548A

公开(公告)日：1996-02-06

申请号：US283871

申请日：1994-08-01

申请人： Yasushiro Nishioka ,  Scott R. Summerfelt ,  Kyung-Ho Park ,  Pijush Bhattacharya

发明人： Yasushiro Nishioka ,  Scott R. Summerfelt ,  Kyung-Ho Park ,  Pijush Bhattacharya

IPC分类号： H01L21/02 ,  H01L29/51 ,  H01L29/92 ,  H01L21/283

CPC分类号： H01L29/516 ,  H01L28/60 ,  H01L28/55

摘要： Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to form a top surface with rounded corners on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.2 40) and a top surface, with the sidewall spacer causing the top surface to have a rounded corner. The rounded corner of the top surface minimizes crack formation in the high-dielectric-constant material layer.

摘要翻译： 通常，本发明利用包括侧壁间隔物的下电极来形成具有圆角的顶表面，在其上可沉积HDC材料而没有实质的开裂。 本发明的一个重要方面是，与不含侧壁间隔物的下电极相似的结构相比，侧壁间隔物不会减小下电极和HDC材料层之间的电接触表面积。 本发明的一个实施例是一种微电子结构，其包括具有主表面的支撑层（例如Si衬底30），覆盖在支撑层的主表面上的下电极和高介电常数材料层（例如BST 44 ）覆盖下电极的顶表面。 下电极包括粘合层（例如TiN 36），非反应层（例如Pt 42），侧壁间隔物（例如SiO 2 40）和顶表面，侧壁间隔物使顶表面具有圆角。 顶表面的圆角最小化高介电常数材料层中的裂纹形成。

公开(公告)号：US5393352A

公开(公告)日：1995-02-28

申请号：US127222

申请日：1993-09-27

申请人： Scott R. Summerfelt

发明人： Scott R. Summerfelt

IPC分类号： C23C14/08 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H05K1/03 ,  H01L29/12

CPC分类号： H01L21/28185 ,  H01L21/02197 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/314 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  Y10S148/014 ,  Y10S148/118 ,  Y10S438/967

摘要： This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick. A second non-Pb/Bi-containing high-dielectric constant oxide layer 30 may be grown on top of the Pb/Bi-containing high-dielectric constant oxide and a conducting layer (top electrode 32) may also be grown on the second non-Pb/Bi-containing high-dielectric constant oxide layer.

摘要翻译： 这是用于制造在半导体电路中有用的结构的方法。 该方法包括：在半导体衬底上直接或间接生长非Pb / Bi的高介电常数氧化物层的缓冲层; 以及在所述缓冲层上沉积含Pb / Bi的高介电常数氧化物。 或者，这可以是在半导体电路中有用的结构，其包括：直接或间接地在半导体衬底10上的非含铅高介电常数氧化物层的缓冲层26; 和在缓冲层上的含铅高介电常数氧化物28。 优选地，在半导体衬底上外延生长锗层12，并且在锗层上生长缓冲层。 当衬底是硅时，非Pb / Bi的高介电常数氧化物层的厚度优选小于约10nm。 可以在含Pb / Bi的高介电常数氧化物的顶部上生长第二非Pb / Bi的高介电常数氧化物层30，并且还可以在第二非绝缘材料上生长导电层（顶电极32） -Pb / Bi高介电常数氧化物层。

公开(公告)号：US5238530A

公开(公告)日：1993-08-24

申请号：US871863

申请日：1992-04-20

申请人： Monte A. Douglas ,  Howard R. Beratan ,  Scott R. Summerfelt

发明人： Monte A. Douglas ,  Howard R. Beratan ,  Scott R. Summerfelt

IPC分类号： C04B41/53 ,  C04B41/91 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L28/55 ,  C04B41/5353 ,  C04B41/91 ,  H01L21/31111

摘要： A titanate substrate (e.g. lead zirconate titanate 34) is immersed in a liquid ambient (e.g. 12 molar concentration hydrochloric acid 30) and illuminated with radiation (e.g. collimated visible/ultraviolet radiation 24) produced by a radiation source (e.g. a 200 Watt mercury xenon arc lamp 20). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the titanate substrate 34. An etch mask 32 may be positioned between the radiation source 20 and the substrate 34. The titanate substrate 34 and liquid ambient 30 are maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the titanate is not appreciably etched by the liquid ambient. Upon illumination the etch rate is substantially increased.

摘要翻译： 将钛酸酯基材（例如锆钛酸铅34）浸入液体环境（例如12摩尔浓度的盐酸30）中，并用辐射源（例如200瓦汞氙）产生的辐射（例如准直的可见/紫外线辐射24）照射 弧光灯20）。 对准直辐射24基本上透明的窗口26允许辐射能量到达钛酸盐衬底34.蚀刻掩模32可以位于辐射源20和衬底34之间。钛酸盐衬底34和液态环境30被保持 在标称温度（例如25℃）下。 在没有照明的情况下，钛酸盐不被液体环境明显腐蚀。 在照射时，蚀刻速率显着增加。

公开(公告)号：US5201989A

公开(公告)日：1993-04-13

申请号：US872701

申请日：1992-04-20

申请人： Monte A. Douglas ,  Howard R. Beratan ,  Scott R. Summerfelt

发明人： Monte A. Douglas ,  Howard R. Beratan ,  Scott R. Summerfelt

IPC分类号： B01J19/12 ,  C01G33/00 ,  C04B41/53 ,  C04B41/91 ,  C23F1/04 ,  C23F1/30 ,  H01L21/02 ,  H01L21/311

CPC分类号： C04B41/009 ,  C04B41/5353 ,  C04B41/91 ,  H01L21/31111 ,  H01L28/40 ,  C04B2111/00387 ,  H01L28/55

摘要： A niobium pentoxide substrate 34 immersed in a liquid ambient (e.g. 10% hydrofluoric acid 30) and illuminated with radiation (e.g. collimated visible/ultraviolet radiation 24) produced by a radiation source (e.g. a 200 Watt mercury xenon arc lamp 20). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the Nb.sub.2 O.sub.5 substrate 34. An etch mask (e.g. organic photoresist 32) may be positioned between the radiation source 20 and the substrate 34. The Nb.sub.2 O.sub.5 substrate 34 and liquid ambient 30 are maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the Nb.sub.2 O.sub.5 is not appreciably etched by the liquid ambient. Upon illumination the etch rate is substantially increased.

摘要翻译： 浸渍在液体环境（例如10％氢氟酸30）中并用辐射源（例如，200瓦汞氙弧灯20）产生的辐射（例如准直的可见/紫外线辐射24）照射的五氧化二铌衬底34。 对准直辐射24基本透明的窗口26允许辐射能量到达Nb 2 O 5衬底34.蚀刻掩模（例如有机光致抗蚀剂32）可以位于辐射源20和衬底34之间.Nb 2 O 5衬底34和 液体环境30保持在标称温度（例如25℃）。 在没有照明的情况下，Nb 2 O 5不被液体环境明显腐蚀。 在照射时，蚀刻速率显着增加。