公开(公告)号：US20240222483A1

公开(公告)日：2024-07-04

申请号：US18091211

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Kevin O’Brien ,  Chelsey Dorow ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Matthew Metz ,  Scott B. Clendenning ,  Chia-Ching Lin ,  Ande Kitamura ,  Mahmut Sami Kavrik

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L21/0257 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: A transistor structure includes a stack of nanoribbons spanning between terminals of the transistor. Ends of the nanoribbons include silicon, and channel regions between the ends include a transition metal and a chalcogen. A gate structure over the channel regions includes an insulator between the channel regions and a gate electrode material. Contact regions may be formed by modifying portions of the channel regions by adding a dopant to, or altering the crystal structure of, the channel regions. The transistor structure may be in an integrated circuit device.

公开(公告)号：US20240222461A1

公开(公告)日：2024-07-04

申请号：US18091201

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Ande Kitamura ,  Carl H. Naylor ,  Kevin O'Brien ,  Kirby Maxey ,  Chelsey Dorow ,  Ashish Verma Penumatcha ,  Scott B. Clendenning ,  Uygar Avci ,  Matthew Metz ,  Chia-Ching Lin ,  Sudarat Lee ,  Mahmut Sami Kavrik ,  Carly Rogan ,  Paul Gutwin

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/443 ,  H01L23/528 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/775

CPC classification number: H01L29/45 ,  H01L21/02568 ,  H01L21/443 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/775

Abstract: A transistor in an integrated circuit (IC) die includes source and drain terminals having a bulk material enclosed by a liner material. A nanoribbon channel region couples the source and drain terminals. The nanoribbon may include a transition metal and a chalcogen. The liner material may contact ends and upper and lower surfaces of the nanoribbon. The transistor may be in an interconnect layer. The source and drain terminals may be formed by conformally depositing the liner material over the ends of the nanoribbon and in voids opened in the IC die.

公开(公告)号：US20240222126A1

公开(公告)日：2024-07-04

申请号：US18147644

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar Avci ,  Brandon Holybee ,  Jennifer Lux ,  Kevin O'Brien ,  Shida Tan

IPC: H01L21/266 ,  H01L21/265

CPC classification number: H01L21/266 ,  H01L21/26506

Abstract: This disclosure describes systems, apparatus, methods, and devices related to fabrication using ion beams. The device may apply an ion beam targeted to at least one of one or more regions of a top layer, a metal layer placed on top of the top layer, or one or more ion stoppers placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify the material characteristics of the 2D material at the one or more regions of the top layer. The device may create a bond between the one or more 2D and metal layers to the one or more regions of the top layer where the material characteristics of the 2D material have been modified due to the impinging ion beam.

公开(公告)号：US20240222113A1

公开(公告)日：2024-07-04

申请号：US18091279

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Kevin OBrien ,  Chelsey Dorow ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Matthew Metz ,  Scott B. Clendenning ,  Mahmut Sami Kavrik ,  Chia-Ching Lin ,  Ande Kitamura

IPC: H01L21/02 ,  H01L21/04 ,  H01L23/31

CPC classification number: H01L21/02568 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/045 ,  H01L23/3171

Abstract: Integrated circuit (IC) structures comprising transistors with metal chalcogenide channel material synthesized on a workpiece comprising a Group IV crystal. Prior to synthesis of the metal chalcogenide material, a passivation material is formed over the Group IV crystal to limit exposure of the substrate to the growth precursor gas(es) and thereby reduce a quantity of chalcogen species subsequently degassed from the workpiece. The passivation material may be applied to the front side, back side, and/or edge of a workpiece. The passivation material may be sacrificial or retained as a permanent feature of an IC structure. The passivation material may be advantageously amorphous and/or a compound comprising at least one of a metal or nitrogen that is good diffusion barrier and thermally stable at the metal chalcogenide synthesis temperatures.

公开(公告)号：US20240222073A1

公开(公告)日：2024-07-04

申请号：US18147636

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Shida Tan ,  Uygar Avci ,  Brandon Holybee ,  Kirby Maxey ,  Kevin O'Brien ,  Mahmut Sami Kavrik

IPC: H01J37/317 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01J37/3174 ,  H01L21/0279 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139 ,  H01J2237/3174 ,  H01J2237/31755

Abstract: This disclosure describes systems, apparatus, methods, and devices related to ion beams fabrication. A device may overlay a wafer assembly of one or more layers with a top layer comprised of a material having 2D material characteristics. The device may be fabricated by applying an ion beam targeted to at least one of one or more regions of the top layer or a resist layer placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify material characteristics of the resist layer or to perform milling of the top layer or other layers of the one or more layers of the wafer assembly.

公开(公告)号：US20240112714A1

公开(公告)日：2024-04-04

申请号：US17957591

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Christopher Neumann ,  Brian Doyle ,  Sou-Chi Chang ,  Bernal Granados Alpizar ,  Sarah Atanasov ,  Matthew Metz ,  Uygar Avci ,  Jack Kavalieros ,  Shriram Shivaraman

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

CPC classification number: G11C11/221 ,  H01L27/11507 ,  H01L28/55

Abstract: A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.

公开(公告)号：US11901400B2

公开(公告)日：2024-02-13

申请号：US16369737

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Owen Loh ,  Mengcheng Lu ,  Seung Hoon Sung ,  Ian A. Young ,  Uygar Avci ,  Jack T. Kavalieros

IPC: H01L49/02 ,  H01G4/012 ,  H01G4/30 ,  H01L23/522 ,  H10B51/00

CPC classification number: H01L28/56 ,  H01G4/012 ,  H01G4/30 ,  H01L23/5226 ,  H10B51/00

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

公开(公告)号：US11862715B2

公开(公告)日：2024-01-02

申请号：US17745822

申请日：2022-05-16

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US11723188B2

公开(公告)日：2023-08-08

申请号：US16024578

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Uygar Avci ,  Ian Young ,  Daniel Morris ,  Seiyon Kim ,  Yih Wang ,  Ruth Brain

IPC: H01L23/522 ,  H01L21/768 ,  H10B12/00 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L21/76808 ,  H01L21/76843 ,  H01L23/5226 ,  H01L28/91 ,  H10B12/033 ,  H10B12/50

Abstract: Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

公开(公告)号：US11640984B2

公开(公告)日：2023-05-02

申请号：US16363952

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Chia-Ching Lin ,  Owen Loh ,  Seung Hoon Sung ,  Aditya Kasukurti ,  Sou-Chi Chang ,  Tanay Gosavi ,  Ashish Verma Penumatcha

IPC: H01L29/51 ,  H01L29/78

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.