公开(公告)号：US08940558B2

公开(公告)日：2015-01-27

申请号：US13836478

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Wilfried E. A. Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Kern Rim

IPC: H01L21/66 ,  G01B7/06

CPC classification number: H01L22/12 ,  G01B7/08 ,  G01B2210/56 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0886

Abstract: Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices.

Abstract translation: 提供了在FINFET技术中量化Dgr Dfin的技术。 一方面，一对用于量化一对长沟道FINFET器件之间的Dgr D D的方法包括以下步骤：（a）获得该对中的每个长沟道FINFET器件的Vth值; （b）确定一对长沟道FINFET器件的“Dgr”Vth; 并且（c）使用＆Dgr; Vth来确定一对长沟道FINFET器件之间的Dgr D D D，其中＆Dgr; Vth是Q对之间的差异和一对长沟道FINFET器件之间的栅极电容的函数 ，并且其中Qbody对于该对中的每个长沟道FINFET器件的Dfin和Nch的函数，并且因此＆Dgr; Vth与该对长沟道FINFET器件之间的＆Dgr; Dfin成比例。

公开(公告)号：US08927397B2

公开(公告)日：2015-01-06

申请号：US13761453

申请日：2013-02-07

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L21/20 ,  H01L21/36 ,  H01L29/66 ,  H01L27/12 ,  B82Y10/00 ,  B82Y99/00

CPC classification number: H01L29/66545 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/888 ,  Y10S977/938

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract translation: 一种制造电子装置的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中图案化至少一个第一/第二组纳米线和焊盘。 围绕用作晶体管器件的沟道区的第一组纳米线的每一个的一部分选择性地形成共形栅介质层。 第一金属栅极堆叠形成在共形栅极介电层上，围绕作为晶体管器件的沟道区域的第一组纳米线的每一个的栅极全部构型。 形成第二金属栅极叠层，围绕作为二极管器件的栅极全部配置的沟道区的第二组纳米线的每一个的一部分。

公开(公告)号：US08896063B2

公开(公告)日：2014-11-25

申请号：US14029306

申请日：2013-09-17

Applicant: International Business Machines Corporation

Inventor： Thomas N. Adam ,  Veeraraghavan S. Basker ,  Jinghong Li ,  Chung-Hsun Lin ,  Sebastian Naczas ,  Alexander Reznicek ,  Tenko Yamashita

IPC: H01L27/12 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers.

Abstract translation: 形成从半导体材料部分延伸的多个半导体散热片，半导体材料部分存在于绝缘体上半导体基板的绝缘体层顶部。 形成跨越每个半导体鳍片的栅极结构和相邻栅极间隔物。 每个半导体鳍片的部分被暴露。 然后通过从未被栅极结构和栅极间隔物覆盖的暴露的半导体材料部分形成外延半导体材料来合并半导体鳍片的露出部分。

公开(公告)号：US20140273298A1

公开(公告)日：2014-09-18

申请号：US13836478

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wilfried E.A. Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Kern Rim

IPC: G01B7/06 ,  H01L21/66

CPC classification number: H01L22/12 ,  G01B7/08 ,  G01B2210/56 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0886

Abstract: Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices.

Abstract translation: 提供了在FINFET技术中量化Dgr Dfin的技术。 一方面，一对用于量化一对长沟道FINFET器件之间的Dgr D D的方法包括以下步骤：（a）获得该对中的每个长沟道FINFET器件的Vth值; （b）确定一对长沟道FINFET器件的“Dgr”Vth; 并且（c）使用＆Dgr; Vth来确定一对长沟道FINFET器件之间的Dgr D D D，其中＆Dgr; Vth是Q对之间的差异和一对长沟道FINFET器件之间的栅极电容的函数 ，并且其中Qbody对于该对中的每个长沟道FINFET器件的Dfin和Nch的函数，并且因此＆Dgr; Vth与该对长沟道FINFET器件之间的＆Dgr; Dfin成比例。

公开(公告)号：US20140217507A1

公开(公告)日：2014-08-07

申请号：US13761453

申请日：2013-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L27/12

CPC classification number: H01L29/66545 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/888 ,  Y10S977/938

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract translation: 一种制造电子装置的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中图案化至少一个第一/第二组纳米线和焊盘。 围绕用作晶体管器件的沟道区的第一组纳米线的每一个的一部分选择性地形成共形栅介质层。 第一金属栅极堆叠形成在共形栅极介电层上，围绕作为晶体管器件的沟道区域的第一组纳米线的每一个的栅极全部构型。 形成第二金属栅极叠层，围绕作为二极管器件的栅极全部配置的沟道区的第二组纳米线的每一个的一部分。

公开(公告)号：US08736023B2

公开(公告)日：2014-05-27

申请号：US13775369

申请日：2013-02-25

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

IPC: H01L29/772 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/42368 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66477

Abstract: A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.

Abstract translation: 一种用于形成场效应晶体管（FET）器件的方法，包括在衬底上形成电介质层，在电介质层上形成第一金属层，去除第一金属层的一部分以露出电介质层的一部分，形成 在所述电介质层和所述第一金属层上的第二金属层，以及去除所述第一金属层和所述第二金属层的一部分，以限定第一FET器件和第二FET器件之间的边界区域。

公开(公告)号：US20130023093A1

公开(公告)日：2013-01-24

申请号：US13628169

申请日：2012-09-27

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Josephine B. Chang

IPC: H01L21/336 ,  H01L21/283

CPC classification number: H01L29/66795 ,  H01L29/66636 ,  H01L29/785

Abstract: A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h1); forming a gate structure over the substrate, the gate structure having a length, a width and a height, the gate structure being perpendicular to the channel structure and being formed over the channel structure such that the channel structure passes through the width of the gate structure, where the height of the gate structure is greater than h1; reducing the height of the channel structure external to the gate structure so as to have a second height (h2); and depositing a silicide layer at least partially over the at least one channel structure external to the gate structure.

Abstract translation: 一种制造晶体管的方法，包括在衬底上形成至少一个导电沟道结构，所述沟道具有长度，宽度和第一高度（h1）; 在所述衬底上形成栅极结构，所述栅极结构具有长度，宽度和高度，所述栅极结构垂直于所述沟道结构并且形成在所述沟道结构上，使得所述沟道结构穿过所述栅极结构的宽度 ，其中栅极结构的高度大于h1; 减小栅极结构外部的沟道结构的高度以便具有第二高度（h2）; 以及至少部分地在所述栅极结构外部的所述至少一个沟道结构上沉积硅化物层。

公开(公告)号：US20190296120A1

公开(公告)日：2019-09-26

申请号：US16440106

申请日：2019-06-13

Applicant: International Business Machines Corporation

Inventor： Anthony I. CHOU ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/426 ,  H01L21/84 ,  H01L21/324 ,  H01L29/51 ,  H01L21/3115 ,  H01L29/40 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/308

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20190043754A1

公开(公告)日：2019-02-07

申请号：US16144433

申请日：2018-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Markus Brink ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/768 ,  H01L23/532 ,  G03F7/00 ,  H01L23/522 ,  H01L21/311 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L21/76807 ,  G03F7/0002 ,  H01L21/02118 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.

公开(公告)号：US09837319B2

公开(公告)日：2017-12-05

申请号：US15076036

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/426 ,  H01L21/3115 ,  H01L21/324 ,  H01L29/40 ,  H01L21/84

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.