公开(公告)号：US07759716B2

公开(公告)日：2010-07-20

申请号：US12116150

申请日：2008-05-06

申请人： Seung-Duk Baek ,  Sun-Won Kang

发明人： Seung-Duk Baek ,  Sun-Won Kang

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L27/088 ,  H01L31/113

CPC分类号： H01L23/5382 ,  H01L23/481 ,  H01L23/5258 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/4813 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device in which a plurality of chips can be reliably stacked without reducing integration thereof. The semiconductor device includes a substrate on which a circuit is provided. Pads are disposed on the substrate for testing the circuit. At least one terminal is provided on the substrate. First conductors are used to electrically couple the pads and the circuit. Second conductors are used to electrically couple the at least one terminal and the circuit. A switching element is disposed in the middle of the first conductors to control the electrical connection between the pads and the circuit. A plurality of semiconductor devices may be stacked on top of one another to form a stacked module, wherein chip selection lines are formed, which extend to the bottom of each of the semiconductor devices to electrically couple chip selection terminals from among the at least one terminal of the semiconductor devices.

摘要翻译： 可以可靠地层叠多个芯片而不降低其一体化的半导体装置。 半导体器件包括其上设置有电路的衬底。 垫片设置在基板上用于测试电路。 在基板上设置至少一个端子。 第一导体用于电连接焊盘和电路。 第二导体用于电耦合至少一个端子和电路。 开关元件设置在第一导体的中间，以控制焊盘和电路之间的电连接。 多个半导体器件可以堆叠在彼此的顶部以形成堆叠的模块，其中形成芯片选择线，其延伸到每个半导体器件的底部，以将芯片选择端子从至少一个端子 的半导体器件。

公开(公告)号：US07598607B2

公开(公告)日：2009-10-06

申请号：US12123367

申请日：2008-05-19

申请人： Hyun-Soo Chung ,  Dong-Hyeon Jang ,  Nam-Seog Kim ,  Sun-Won Kang

发明人： Hyun-Soo Chung ,  Dong-Hyeon Jang ,  Nam-Seog Kim ,  Sun-Won Kang

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

摘要： Provided is a semiconductor package with enhanced joint reliability and methods of fabricating the same. The method includes: forming package units including a semiconductor chip interposed between a bottom layer and a top layer; and sequentially stacking the package units on a substrate. The bottom layer and the top layer are formed of a material having a lower modulus than the semiconductor chip. The semiconductor package includes: at least one package unit disposed on a substrate, the package unit including a semiconductor chip having a pad, a bottom layer and a top layer substantially surrounding the semiconductor chip, and a redistribution structure overlying the top layer. The redistribution structure is electrically connected to the pad.

摘要翻译： 提供了具有增强的接头可靠性的半导体封装以及其制造方法。 该方法包括：形成包括插入在底层和顶层之间的半导体芯片的封装单元; 并且将所述封装单元依次堆叠在基板上。 底层和顶层由具有比半导体芯片低的模量的材料形成。 所述半导体封装包括：设置在基板上的至少一个封装单元，所述封装单元包括具有衬垫，底层和基本上围绕所述半导体芯片的顶层的半导体芯片以及覆盖所述顶层的再分布结构。 再分配结构电连接到焊盘。

公开(公告)号：US20090109642A1

公开(公告)日：2009-04-30

申请号：US12249047

申请日：2008-10-10

申请人： Hyun-Soo Chung ,  Dong-Ho Lee ,  Seong-Deok Hwang ,  Sun-Won Kang ,  Ki-Hyuk Kim

发明人： Hyun-Soo Chung ,  Dong-Ho Lee ,  Seong-Deok Hwang ,  Sun-Won Kang ,  Ki-Hyuk Kim

IPC分类号： H05K7/00

CPC分类号： H05K1/0271 ,  H01L23/498 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2924/12044 ,  H05K1/181 ,  H05K2201/0133 ,  H05K2201/10674 ,  H05K2203/1572

摘要： Semiconductor devices and electronic devices using the same. The semiconductor module may include a first semiconductor chip, and a module substrate having a top surface on which the first semiconductor chip is mounted and a second surface opposite the top surface, wherein the module substrate includes a first buffer layer to relieve stress occurring due to a difference of thermal expansions between the first semiconductor chip and the module substrate.

摘要翻译： 半导体器件和使用其的电子器件。 半导体模块可以包括第一半导体芯片和具有安装有第一半导体芯片的顶表面的模块衬底和与顶表面相对的第二表面，其中模块衬底包括第一缓冲层，以缓解由于 第一半导体芯片和模块基板之间的热膨胀差异。

公开(公告)号：US07196532B2

公开(公告)日：2007-03-27

申请号：US11146981

申请日：2005-06-06

申请人： Sun-Won Kang

发明人： Sun-Won Kang

IPC分类号： G01R31/02

CPC分类号： G01R1/06733 ,  G01R1/06738

摘要： An embodiment may comprise a test probe to measure electrical properties of a semiconductor package having ball-shaped terminals. The probe may include a signal tip and a ground tip. The signal tip may have a spherical lower surface allowing good contact with a ball-shaped signal terminal. The ground tip may be extended from a lower end of a ground barrel that encloses the signal tip. The ground tip may move independent of the signal tip by means of a barrel stopper and a spring. Thus, the probe can be used regardless of the size of and the distance between the package terminals.

摘要翻译： 实施例可以包括用于测量具有球形端子的半导体封装的电特性的测试探针。 探头可以包括信号尖端和接地尖端。 信号尖端可以具有允许与球形信号端子良好接触的球形下表面。 接地尖端可以从包围信号尖端的接地筒的下端延伸。 接地尖端可以通过镜筒塞和弹簧独立于信号尖端移动。 因此，可以使用探针，而不管封装端子之间的尺寸和距离。

公开(公告)号：US20060138648A1

公开(公告)日：2006-06-29

申请号：US11305282

申请日：2005-12-16

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

IPC分类号： H01L23/34

CPC分类号： H01L25/105 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19107 ,  H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

摘要翻译： 提供一种不具有焊球的半导体封装模块和制造该半导体封装模块的方法。 该半导体封装模块包括：模块板，多个半导体器件能够安装在该模块板上;半导体封装，使用粘合剂结合在模块板上，可与模块板接合，并且已经经过电气最终测试 ，将所述半导体封装的第二接合焊盘与所述模块板的焊盘电连接的第二布线; 以及封装第二导线和半导体封装的第三密封树脂。 由于半导体封装模块不使用焊球，因此可以防止焊点可靠性（SJR）的劣化。 此外，使用已经经历电测试的半导体封装可以降低完成的半导体封装模块的产量的劣化。

公开(公告)号：US20050280432A1

公开(公告)日：2005-12-22

申请号：US11146981

申请日：2005-06-06

申请人： Sun-Won Kang

发明人： Sun-Won Kang

IPC分类号： G01R1/067 ,  G01R31/02

CPC分类号： G01R1/06733 ,  G01R1/06738

摘要： An embodiment may comprise a test probe to measure electrical properties of a semiconductor package having ball-shaped terminals. The probe may include a signal tip and a ground tip. The signal tip may have a spherical lower surface allowing good contact with a ball-shaped signal terminal. The ground tip may be extended from a lower end of a ground barrel that encloses the signal tip. The ground tip may move independent of the signal tip by means of a barrel stopper and a spring. Thus, the probe can be used regardless of the size of and the distance between the package terminals.

摘要翻译： 实施例可以包括用于测量具有球形端子的半导体封装的电特性的测试探针。 探头可以包括信号尖端和接地尖端。 信号尖端可以具有允许与球形信号端子良好接触的球形下表面。 接地尖端可以从包围信号尖端的接地筒的下端延伸。 接地尖端可以通过镜筒塞和弹簧独立于信号尖端移动。 因此，可以使用探针，而不管封装端子之间的尺寸和距离。

公开(公告)号：US20130168842A1

公开(公告)日：2013-07-04

申请号：US13610077

申请日：2012-09-11

申请人： Chul PARK ,  Sun-Won Kang ,  Kil-Soo Kim ,  Joong-Hyun Baek

发明人： Chul PARK ,  Sun-Won Kang ,  Kil-Soo Kim ,  Joong-Hyun Baek

IPC分类号： H01L23/48

CPC分类号： H01L23/4951 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package includes a semiconductor chip stack disposed between first and second leads near first and second sides of the package and including a plurality of semiconductor chips, and a redistribution structure disposed on the semiconductor chip stack. At least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near or closer to a third side of the package. The redistribution structure includes a first redistribution pad disposed near or closer to the first side and electrically connected to the first lead, a second redistribution pad disposed near or closer to the second side and electrically connected to the second lead, and a third redistribution pad disposed near or closer to the third side and electrically connected to a first one of the first chip pads and the first redistribution pad.

摘要翻译： 半导体封装包括设置在封装的第一和第二侧附近的第一和第二引线之间的半导体芯片堆叠，并且包括多个半导体芯片以及设置在半导体芯片堆叠上的再分配结构。 半导体芯片堆叠的至少一个半导体芯片包括设置在封装的第三侧附近或更接近第三侧的多个第一芯片焊盘。 再分配结构包括设置在第一侧附近或更靠近第一侧并且电连接到第一引线的第一再分配焊盘，设置在第二侧附近或更靠近第二侧并与第二引线电连接的第二再分配焊盘，以及布置 靠近或更靠近第三侧并且电连接到第一芯片焊盘和第一再分布焊盘中的第一芯片焊盘。

公开(公告)号：US20120104631A1

公开(公告)日：2012-05-03

申请号：US13344803

申请日：2012-01-06

申请人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

发明人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

摘要翻译： 半导体模块可以包括在电路基板上具有第一裸片的电路基板和在第一裸片上的第二裸片。 第一裸片可以包括在第一裸片的第一周边部分上的至少一个第一数据输入/输出焊盘和第三外围部分上的至少一个第一控制/地址焊盘，第三外围部分与第一外围部分的第一外围部分分离 第一个死亡 第二管芯可以包括在第二外围部分上的至少一个第二数据输入/输出焊盘和第四外围部分上的至少一个第二控制/地址焊盘。 第二模具的第二周边部分在平面图中不与第一模具的第一周边部分重叠。 第二模具的第四周边部分与第一模具的第三周边部分的至少一部分重叠。

公开(公告)号：US08097940B2

公开(公告)日：2012-01-17

申请号：US12588382

申请日：2009-10-14

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad.

摘要翻译： 堆叠包装可以包括具有彼此相对的第一和第二面以及其中形成的开口的衬底。 第一半导体芯片可以安装在基板的第一面上，并且在通过开口暴露的第一半导体芯片的中间区域中包括通孔。 第二半导体芯片可以堆叠在第一半导体芯片上并且通过第一半导体芯片的通孔电连接到第一半导体芯片。 电路图案可以形成在基板的第二面上，并且包括邻近开口布置的焊盘，并且通过开口与第一半导体芯片的通孔电连接，与焊盘间隔开的外连接焊盘和 连接配线，从连接焊盘的开口延伸到外部连接焊盘。

公开(公告)号：US20110169173A1

公开(公告)日：2011-07-14

申请号：US13005051

申请日：2011-01-12

申请人： Sung-Ho MUN ,  Sun-Won Kang

发明人： Sung-Ho MUN ,  Sun-Won Kang

IPC分类号： H01L23/48

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/85196 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A wiring substrate for a semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface. The substrate has at least one slot from the first surface to the second surface that exposes chip pads of a semiconductor chip mounted to the first surface. The substrate has first and second regions divided by the slot. A plurality of bonding pads is arranged along both side portions of the slot and the bonding pads are connected to bonding wires that are drawn from the chip pads through the slot. First and second conductive patterns are respectively formed in the first and second regions and respectively connected to the at least one bonding pad. A merging pattern extends from the first region to the second region to electrically connect the first conductive pattern and the second conductive pattern. A merging wire electrically connects the merging pattern and the at least one chip pad.

摘要翻译： 用于半导体芯片的布线基板包括具有与第一表面相对的第一表面和第二表面的基板。 衬底具有从第一表面到第二表面的至少一个槽，其暴露安装到第一表面的半导体芯片的芯片焊盘。 衬底具有由槽划分的第一和第二区域。 多个接合焊盘沿着槽的两侧布置，并且焊盘与从芯片焊盘通过槽拉出的接合线连接。 第一和第二导电图案分别形成在第一和第二区域中，并且分别连接到至少一个接合焊盘。 合并图案从第一区域延伸到第二区域以电连接第一导电图案和第二导电图案。 合并线将合并图案与至少一个芯片垫电连接。