公开(公告)号：US5327374A

公开(公告)日：1994-07-05

申请号：US956896

申请日：1992-12-29

Applicant: Wolfgang Krautschneider ,  Klaus Lau ,  Lothar Risch

Inventor： Wolfgang Krautschneider ,  Klaus Lau ,  Lothar Risch

IPC: H01L27/10 ,  G11C5/00 ,  G11C11/402 ,  G11C11/404 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/06 ,  G11C7/00

CPC classification number: G11C11/405 ,  G11C11/404 ,  G11C5/005 ,  H01L27/108

Abstract: An arrangement with self-amplifying dynamic MOS transistor storage cells has in each case a MOS selection transistor AT, whose gate is connected to a word line WL, and an MOS storage transistor ST at whose gate a capacitor C for charge storage acts. This self-amplifying storage cell can be written on and read out with only one bit line BL and one word line WL. The two transistors AT and ST are connected in series and a common drain source region DS is connected via a voltage-dependent resistor VR to the gate electrode GST of the control transistor. The advantages reside in the fact that the cell geometry can be scaled without at the same time the quantity Q of charge which can be read out on the bit line BL having to be reduced, in that the quantity Q of charge which can be read out is larger than a charge stored in the capacitor C which acts at the gate of the storage transistor ST and in that the two MOS transistors AT and ST can be produced relatively simply.

Abstract translation: PCT No.PCT / DE91 / 00502 Sec。 371日期1992年12月29日 102（e）1992年12月29日PCT PCT 1991年7月18日PCT公布。 公开号WO92 / 01287 日本1992年1月23日。具有自放大动态MOS晶体管存储单元的布置在每种情况下都是MOS选择晶体管AT，其栅极连接到字线WL，MOS存储晶体管ST在其栅极处具有电容器C 用于充电存储动作。 该自放大存储单元可以仅用一个位线BL和一个字线WL写入和读出。 两个晶体管AT和ST串联连接，并且公共漏极源极区域DS经由电压依赖电阻器VR连接到控制晶体管的栅电极GST。 优点在于，可以对单元几何形状进行缩放，而不必同时在位线BL上读出的电荷量Q必须减小，因为可以读出的电荷量Q 大于存储在存储晶体管ST的栅极处的电容器C中存储的电荷，并且可以相对简单地制造两个MOS晶体管AT和ST。

公开(公告)号：US4331709A

公开(公告)日：1982-05-25

申请号：US171180

申请日：1980-07-22

Applicant: Lothar Risch ,  Erich Pammer ,  Karlheinz Friedrich

Inventor： Lothar Risch ,  Erich Pammer ,  Karlheinz Friedrich

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/324 ,  H01L21/339 ,  H01L23/29 ,  H01L29/51 ,  H01L29/76 ,  H01L29/762 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L21/314 ,  H01L21/3185 ,  H01L21/324 ,  H01L23/291 ,  H01L23/298 ,  H01L29/518 ,  H01L21/28194 ,  H01L2924/0002 ,  Y10S438/91

Abstract: Fast surface states in MOS devices, such as SCCDs, are reduced by depositing a relatively thin amorphous layer containing silicon and hydrogen onto the SiO.sub.2 surface of such devices and annealing the resultant device in a non-oxidizing atmosphere for brief periods of time at a temperature in excess of the deposition temperature for the amorphous layer but below about 500.degree. C. so that free valences at the Si-SiO.sub.2 interface region are saturated with hydrogen. Surface state densities of about 4.times.10.sup.8 cm.sup.-2 eV.sup.-1 and SCCDs having .epsilon.=1.10.sup.-5 can be achieved via this process. The process is useful in producing SCCDs with low surface state densities and other MOS devices having low surface generated dark currents.

Abstract translation: 通过在这样的器件的SiO 2表面上沉积含有硅和氢的相对薄的无定形层，并在非氧化性气氛中在温度下短时间内退火所得到的器件，减少MOS器件（例如SCCD）中的快速表面状态 超过非晶层的沉积温度但低于约500℃，使得Si-SiO 2界面区域处的自由价态被氢饱和。 约4×10 8 cm -2eV-1的表面状态密度和ε= 1.10-5的SCCD可以通过该方法实现。 该方法可用于生产具有低表面状态密度的SCCD和具有低表面产生暗电流的其它MOS器件。

公开(公告)号：US20090225580A1

公开(公告)日：2009-09-10

申请号：US12044849

申请日：2008-03-07

Applicant: Peng-Fei Wang ,  Gill Yong Lee ,  Lothar Risch

Inventor： Peng-Fei Wang ,  Gill Yong Lee ,  Lothar Risch

IPC: G11C5/06 ,  H01L21/71

CPC classification number: H01L27/1021 ,  G11C7/18 ,  H01L27/101 ,  H01L27/1022 ,  H01L27/224 ,  H01L27/226 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

Abstract: An integrated circuit includes a plurality of memory cells, each memory cell including a memory element and a select device; and a plurality of word lines and bit lines connected to the memory cells. The bit lines, word lines, and the memory elements are arranged above the select devices.

Abstract translation: 集成电路包括多个存储器单元，每个存储单元包括存储元件和选择器件; 以及连接到存储单元的多个字线和位线。 位线，字线和存储元件布置在选择器件上方。

公开(公告)号：US07368752B2

公开(公告)日：2008-05-06

申请号：US10839800

申请日：2004-05-06

Applicant: Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

Inventor： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

IPC: H01L27/108 ,  H01L29/12 ,  H01L31/112

CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

Abstract: A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

Abstract translation: DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层 在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器， 所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

公开(公告)号：US20080054324A1

公开(公告)日：2008-03-06

申请号：US11926653

申请日：2007-10-29

Applicant: Richard Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rosner ,  Till Schloesser ,  Michael Specht

Inventor： Richard Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rosner ,  Till Schloesser ,  Michael Specht

IPC: H01L29/94

CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at at least two opposite sides.

Abstract translation: 公开了一种包括栅电极的集成电路。 一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。 在半导体衬底中的第一和第二源极/漏极之间布置有沟道。 栅电极被布置在沟道层附近并且与沟道层电绝缘。 半导体基板电极设置在后侧。 栅电极在至少两个相对的两侧包围沟道层。

公开(公告)号：US06503784B1

公开(公告)日：2003-01-07

申请号：US09670742

申请日：2000-09-27

Applicant: Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

Inventor： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC: H01L218238

CPC classification number: H01L27/11 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1203

Abstract: A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

Abstract translation: 一种具有一对垂直双门控CMOS晶体管的半导体体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06472767B1

公开(公告)日：2002-10-29

申请号：US09302757

申请日：1999-04-30

Applicant: Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

Inventor： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC: H01L2711

CPC classification number: H01L27/11 ,  H01L27/1104

Abstract: A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

Abstract translation: 具有一对垂直双门控CMOS晶体管的半导体本体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06442042B2

公开(公告)日：2002-08-27

申请号：US09883901

申请日：2001-06-18

Applicant: Ties Ramcke ,  Lothar Risch ,  Wolfgang Rösner

Inventor： Ties Ramcke ,  Lothar Risch ,  Wolfgang Rösner

IPC: H05K702

CPC classification number: H01L23/528 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one CMOS component which is configured in a semiconductor substrate is part of the inventive circuit assembly. An insulating layer is configured on the semiconductor substrate. The insulating layer covers the CMOS component. A nanoelectronic component is configured above the insulating layer. At least one conducting structure is configured in the insulating layer and serves to link the nanoelectronic component with the CMOS component. If several nanoelectronic components are provided, they are preferably grouped to nano-circuit blocks. Each of the nano-circuit blocks is so small that the RC times of their lines do not exceed 1 ns.

Abstract translation: 配置在半导体衬底中的至少一个CMOS部件是本发明电路组件的一部分。 绝缘层配置在半导体衬底上。 绝缘层覆盖CMOS元件。 纳米电子部件被配置在绝缘层的上方。 在绝缘层中配置至少一个导电结构，用于将纳米电子部件与CMOS部件连接起来。 如果提供几个纳米电子部件，则它们优选地分组成纳米电路块。 每个纳米电路块都很小，使得它们的线路的RC时间不超过1ns。

公开(公告)号：US06420228B1

公开(公告)日：2002-07-16

申请号：US09851051

申请日：2001-05-08

Applicant: Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

Inventor： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

IPC: H01L218242

CPC classification number: H01L27/10864 ,  H01L27/10841

Abstract: A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.

Abstract translation: DRAM单元配置包括每个存储单元的垂直MOS晶体管。 晶体管的第一源极/漏极区域分别属于两个相邻的晶体管并与位线相邻。 晶体管的第二源/漏区连接到存储节点。 晶体管的栅电极具有由栅极氧化物邻接的正好两侧。 可以通过使用具有4F2的存储单元面积的三个掩模来产生DRAM单元配置。 F是可以通过使用各自技术制造的最小结构尺寸。

公开(公告)号：US06417043B1

公开(公告)日：2002-07-09

申请号：US09528268

申请日：2000-03-17

Applicant: Lothar Risch ,  Wolfgang Rösner ,  Ties Ramcke ,  Hermann Jacobs

Inventor： Lothar Risch ,  Wolfgang Rösner ,  Ties Ramcke ,  Hermann Jacobs

IPC: H01L2976

CPC classification number: H01L21/822 ,  G11C17/10 ,  H01L27/101

Abstract: Resistors are connected between word lines and bit lines running transversely with respect thereto. The resistors have a higher resistance than the word lines and the bit lines. The bit lines are each connected to a sense amplifier which regulates the potential on the respective bit line to a reference potential and at which an output signal can be picked off. If one of the word lines is selected and all the other word lines are put at reference potential, then the resistance of the resistor, which is assigned to an information item, can be read from the output signal.

Abstract translation: 电阻器连接在相对于其横向延伸的字线和位线之间。 电阻器具有比字线和位线更高的电阻。 位线各自连接到读出放大器，其将相应位线上的电位调节到参考电位，并且可以在其处拾取输出信号。 如果选择一条字线并且所有其它字线被置于参考电位，则可以从输出信号中读取分配给信息项的电阻的电阻。