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    Thermal interposer for thermal management of semiconductor devices
    33.
    发明授权
    Thermal interposer for thermal management of semiconductor devices 失效
    用于半导体器件热管理的热插入器

    公开(公告)号：US07180179B2

    公开(公告)日：2007-02-20

    申请号：US10872575

    申请日：2004-06-18

    申请人： Lawrence S. Mok ,  Evan G. Colgan ,  Minhua Lu ,  Da-Yuan Shih

    发明人： Lawrence S. Mok ,  Evan G. Colgan ,  Minhua Lu ,  Da-Yuan Shih

    IPC分类号： H01L23/34 ,  H01L23/495

    CPC分类号： H01L23/427 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10158 ,  H01L2924/15311

    摘要： A thermal interposer is provided for attachment to a surface of a semiconductor device. In one embodiment, the thermal interposer includes an upper plate having a bottom surface with a plurality of grooves and made of a material having high thermal conductivity, and a lower plate having a top surface with a plurality of grooves and made of a material having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the material of a semiconductor device that is bonded to the bottom surface of the lower plate. The bottom surface of the upper plate is hermetically bonded to the top surface of the lower plate so that a vapor chamber is formed by the upper and lower plates, and walls of the grooves on the top surface of the lower plate extend to within less than 250 microns from walls of the grooves on the bottom surface of the upper plate comprise a plurality of second walls the first walls.

    摘要翻译： 提供了用于附接到半导体器件的表面的热插入件。 在一个实施例中，热插入件包括具有多个凹槽并由具有高导热性的材料制成的底表面的上板，以及具有多个凹槽的顶表面的下板，并由具有 热膨胀系数与结合到下板的底面的半导体器件的材料的热膨胀系数基本相同。 上板的底面与下板的顶面密封，从而通过上板和下板形成蒸气室，下板顶表面上的槽的壁延伸到小于 在上板的底表面上的槽的壁250微米包括多个第二壁和第一壁。

    Injection molded microoptics
    34.
    发明申请
    Injection molded microoptics 有权
    注塑微光学

    公开(公告)号：US20070029277A1

    公开(公告)日：2007-02-08

    申请号：US11195147

    申请日：2005-08-02

    申请人： Lawrence Jacobowitz ,  Stephen Buchwalter ,  Casimer DeCusatis ,  Peter Gruber ,  Da-Yuan Shih

    发明人： Lawrence Jacobowitz ,  Stephen Buchwalter ,  Casimer DeCusatis ,  Peter Gruber ,  Da-Yuan Shih

    IPC分类号： B29D11/00 ,  B29C35/08 ,  B29C45/00

    CPC分类号： H01L27/14685 ,  B29D11/00365 ,  B29D11/00461 ,  B82Y30/00 ,  G02B3/0018 ,  G02B3/0056 ,  G02F1/137 ,  G02F1/29 ,  H01L27/14627 ,  H01L31/02327 ,  H01L33/58

    摘要： A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits. The present invention applies to spectral filters, waveguides, fiber-optic mode-transformers, diffraction gratings, refractive lenses, diffractive lens/Fresnel zone plates, reflectors, and to combinations of elements and devices, including microelectromechanical systems (MEMS) and liquid crystal device (LCD) matrices for adaptive, tunable elements. Preparation of interfacial layer properties and attachment process embodiments are taught.

    摘要翻译： 描述了用于在半导体和其他图像显示装置，背板，光电板和集成光学系统上形成，对准和附着微量元件的二维阵列的自动化的晶片级装置和方法。 在有序的制造顺序中，由光学设计的空腔构成的模具板通过反应离子蚀刻或可选的工艺形成，任选地涂覆有释放材料层，并通过自动化流体注入和缺陷检查子系统填充光学特定的材料。 光学校准基准指导所公开的转移和附着过程以实现微光学元件与对应的光电器件和电路之间的特定公差。 本发明适用于光谱滤波器，波导管，光纤模式变压器，衍射光栅，折射透镜，衍射透镜/菲涅耳带片，反射器以及元件和器件的组合，包括微机电系统（MEMS）和液晶器件 （LCD）矩阵，用于自适应，可调元素。 教导界面层性质和附着工艺实施例的制备。

    Structures and processes to create a desired probetip contact geometry on a wafer test probe
    39.
    发明授权
    Structures and processes to create a desired probetip contact geometry on a wafer test probe 失效
    在晶圆测试探针上创建所需的先天触点几何形状的结构和过程

    公开(公告)号：US06206273B1

    公开(公告)日：2001-03-27

    申请号：US09251864

    申请日：1999-02-17

    申请人： Brian Samuel Beaman ,  Keith Edward Fogel ,  Paul Alfred Lauro ,  Da-Yuan Shih

    发明人： Brian Samuel Beaman ,  Keith Edward Fogel ,  Paul Alfred Lauro ,  Da-Yuan Shih

    IPC分类号： B23K3100

    CPC分类号： G01R1/0675 ,  G01R1/07314 ,  G01R3/00 ,  Y10T29/4914

    摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are formed by cutting with one or more blades. The shape of the blades determines the shape of the probetips. The probetips can be coated with other conductive materials to enhance the hardness and profile of protuberances formed at the probetip ends by the blade-cutting process. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer. The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

    摘要翻译： 本发明涉及一种高密度测试探针，其提供用于测试晶片形式的高密度和高性能集成电路或作为离散芯片的装置。 测试探针由细长电导体的密集阵列形成，其通过用一个或多个刀片切割形成。 叶片的形状决定了先兆的形状。 可以使用其他导电材料涂覆先知，以通过叶片切割工艺增强在突齿端部处形成的突起的硬度和轮廓。 电线与接触位置阵列一样密集。 围绕着向外突出的线的阵列设置模具。 液体弹性体设置在模具中以填充电线之间的空间。 弹性体被固化并且模具被去除，留下布置在弹性体中并与空间变压器电接触的线阵列。 空间变压器可以具有一个引脚阵列，它们在空间变压器的与细长导体所接合的相反的表面上。 这些销插入第二空间变压器（例如印刷电路板）上的插座中以形成探针组件。 或者，插入器电连接器可以设置在第一和第二空间变压器之间。