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    MEMORY SYSTEM THAT SUPPORTS DUAL-MODE MODULATION
    32.
    发明申请
    MEMORY SYSTEM THAT SUPPORTS DUAL-MODE MODULATION 审中-公开

    公开(公告)号：US20190103149A1

    公开(公告)日：2019-04-04

    申请号：US15977820

    申请日：2018-05-11

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

    IPC: G11C8/12 ,  G06F12/02

    Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.

    Apparatuses and methods for targeted refreshing of memory
    36.
    发明授权
    Apparatuses and methods for targeted refreshing of memory 有权
    存储器目标刷新的设备和方法

    公开(公告)号：US09324398B2

    公开(公告)日：2016-04-26

    申请号：US13758667

    申请日：2013-02-04

    Applicant: Micron Technology, Inc.

    Inventor： William F. Jones ,  Jeffrey P. Wright

    IPC: G11C8/10 ,  G11C11/406

    CPC classification number: G11C8/10 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4087 ,  G11C17/16 ,  G11C17/18 ,  G11C29/783 ,  G11C2211/4068

    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

    Abstract translation: 本文公开了用于目标行刷新的装置和方法。 在示例性装置中，预解码器接收目标行地址并且确定与目标行地址相关联的目标行存储器是主存储器还是冗余存储器行。 如果主行是目标行或物理上邻近待刷新的存储器的行，存储器的一行或多行存储器将被刷新，则预解码器还被配置为使物理上邻近主行存储器的一行或多行存储器被刷新，如果 内存冗余行是目标行内存。

    APPARATUSES AND METHODS FOR CONTROLLING A CLOCK SIGNAL PROVIDED TO A CLOCK TREE
    37.
    发明申请
    APPARATUSES AND METHODS FOR CONTROLLING A CLOCK SIGNAL PROVIDED TO A CLOCK TREE 有权
    用于控制提供给时钟树的时钟信号的装置和方法

    公开(公告)号：US20150318032A1

    公开(公告)日：2015-11-05

    申请号：US14800512

    申请日：2015-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P. Wright

    IPC: G11C7/22 ,  H03K19/00 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

    Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

    Abstract translation: 描述了用于控制时钟树的时钟信号的装置，感测电路和方法。 一种示例性装置包括一个连续的写入命令检测电路，其被配置为响应于在写入命令寄存器的输出处提供的当前写入命令来检测在当前写入命令的连续写入命令周期内是否接收到下一个写入命令。 该示例设备还包括一个时钟信号控制电路，该时钟信号控制电路耦合到该连续的写命令检测电路，并且被配置为基于该连续的写入命令检测电路是否检测到下一个写入来控制到输入/输出（I / O） 命令在连续写入命令周期内。

    METHODS AND APPARATUSES FOR REFRESHING MEMORY
    38.
    发明申请
    METHODS AND APPARATUSES FOR REFRESHING MEMORY 有权
    刷新记忆的方法和装置

    公开(公告)号：US20140153350A1

    公开(公告)日：2014-06-05

    申请号：US13693865

    申请日：2012-12-04

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aaron P. Boehm ,  Jeffrey P. Wright

    IPC: G11C7/00

    CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40611

    Abstract: Apparatuses and methods for memory refreshing memory cells is described. An example method includes receiving a self refresh command at a memory. The method further includes refreshing the memory at a first refresh rate after receiving the self refresh command. The method further includes refreshing the memory at a second refresh rate in response to a determination that each memory cell of the memory has been refreshed at the first refresh rate. The first refresh rate is greater than a second refresh rate.

    Abstract translation: 描述了用于存储器刷新存储器单元的装置和方法。 一种示例性方法包括在存储器处接收自刷新命令。 该方法还包括在接收到自刷新命令之后以第一刷新速率刷新存储器。 该方法还包括响应于确定存储器的每个存储器单元已经以第一刷新率刷新的第二刷新率刷新存储器。 第一次刷新率大于第二次刷新率。

    VARIABLE MODULATION SCHEME FOR MEMORY DEVICE ACCESS OR OPERATION
    39.
    发明申请
    VARIABLE MODULATION SCHEME FOR MEMORY DEVICE ACCESS OR OPERATION 有权

    公开(公告)号：US20230004492A1

    公开(公告)日：2023-01-05

    申请号：US17863987

    申请日：2022-07-13

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

    IPC: G06F12/0806 ,  H04L5/00

    Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

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