公开(公告)号：US20170178810A1

公开(公告)日：2017-06-22

申请号：US14976973

申请日：2015-12-21

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Daeik Daniel KIM ,  Niranjan Sunil MUDAKATTE ,  Je-Hsiung Jeffrey LAN ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Jonghae KIM

IPC: H01G4/30 ,  H01G4/01

CPC classification number: H01G4/30 ,  H01G4/01 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/87 ,  H01L29/94

Abstract: An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.

公开(公告)号：US20160163450A1

公开(公告)日：2016-06-09

申请号：US15046302

申请日：2016-02-17

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01F41/04

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/29 ,  H01F2017/004 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

Abstract translation: 三维（3D）正交电感器对被嵌入并由衬底支撑，并且具有第一电感器，其具有卷绕第一绕组轴线的第一线圈和具有卷绕第二绕组轴线的第二线圈的第二电感器 。 第二卷绕轴线与第一卷绕轴线正交。 第二绕组轴线在第一绕组轴线处于衬底内的交点处。

公开(公告)号：US20150287677A1

公开(公告)日：2015-10-08

申请号：US14483944

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey LAN ,  David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L21/283

CPC classification number: H01L23/5227 ,  H01L21/283 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L27/01 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.

Abstract translation: 集成电路器件包括衬底。 集成电路器件还包括第一导电叠层，其包括参考衬底的第一高度处的后端行（BEOL）导电层。 集成电路器件还包括第二导电叠层，其包括相对于衬底的第二高度处的BEOL导电层。 第二个高程与第一个高程不同。

公开(公告)号：US20150256143A1

公开(公告)日：2015-09-10

申请号：US14196355

申请日：2014-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Changhan Hobie YUN ,  Chengjie ZUO ,  Jonghae KIM ,  Mario Francisco VELEZ ,  Daeik Daniel KIM ,  Rick Allen WILCOX

IPC: H03H9/02 ,  H03H9/13 ,  H03H3/02 ,  H03H9/46

CPC classification number: H03H9/02448 ,  H03H3/02 ,  H03H9/02133 ,  H03H9/02228 ,  H03H9/02244 ,  H03H9/132 ,  H03H9/133 ,  H03H9/15 ,  H03H9/462 ,  H03H9/54 ,  H03H2003/027

Abstract: An integrated circuit device includes a piezoelectric substrate having a first surface and a second surface opposite the first surface. The device also includes a first electrode and a second electrode on the first surface of the piezoelectric substrate, the first electrode having a first width and the second electrode having a second width. The device further includes a third electrode and a fourth electrode on the second surface of the piezoelectric substrate, the third electrode having a third width that is substantially the same as the second width, and the fourth electrode having a fourth width that is substantially the same as the first width. The first and third electrodes operate as part of a first portion of a microelectromechanical systems (MEMS) resonator, and the second and fourth electrodes operate as part of a second portion of the MEMS resonator.

Abstract translation: 集成电路装置包括具有第一表面和与第一表面相对的第二表面的压电基片。 该装置还包括在压电基片的第一表面上的第一电极和第二电极，第一电极具有第一宽度，第二电极具有第二宽度。 该装置还包括在压电基片的第二表面上的第三电极和第四电极，第三电极具有与第二宽度基本相同的第三宽度，第四电极具有基本相同的第四宽度 作为第一宽度。 第一和第三电极作为微机电系统（MEMS）谐振器的第一部分的一部分工作，第二和第四电极作为MEMS谐振器的第二部分的一部分工作。

公开(公告)号：US20150200245A1

公开(公告)日：2015-07-16

申请号：US14153917

申请日：2014-01-13

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daeik Daniel KIM ,  Chengjie ZUO ,  Mario Francisco VELEZ ,  Jonghae KIM ,  David Francis BERDY

IPC: H01L49/02

CPC classification number: H01L28/88 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lateral metal insulator metal (MIM) capacitor includes a first conductive plate, and a dielectric layer on a sidewall(s) and a first surface of the first conductive plate adjacent to the sidewall(s). The capacitor also includes a second conductive plate on a portion of the dielectric layer that is on the sidewall(s) and on a portion of the dielectric layer that covers a portion of the first surface of the first conductive plate. A sidewall capacitance is also greater than a surface capacitance of the capacitor.

Abstract translation: 横向金属绝缘体金属（MIM）电容器包括第一导电板和侧壁上的介电层以及邻近侧壁的第一导电板的第一表面。 所述电容器还包括位于所述侧壁上以及所述电介质层的覆盖所述第一导电板的所述第一表面的一部分的所述介电层的一部分上的第二导电板。 侧壁电容也大于电容器的表面电容。

公开(公告)号：US20150115777A1

公开(公告)日：2015-04-30

申请号：US14067908

申请日：2013-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Changhan Hobie YUN ,  Chengjie ZUO ,  Mario Francisco VELEZ ,  Daeik Daniel KIM ,  Jonghae KIM

IPC: H03H9/17 ,  H01L41/047

CPC classification number: H03H9/17 ,  H01L41/047 ,  H03H9/02157 ,  H03H9/13 ,  H03H9/56

Abstract: A resonator includes a piezoelectric core, a set of electrodes, and at least one ground terminal. The electrodes are arranged on the piezoelectric core and also includes at least one input electrode having a first width and at least one output electrode having a second width that differs from the first width. The ground terminal is also on the piezoelectric core.

Abstract translation: 谐振器包括压电芯，一组电极和至少一个接地端子。 电极布置在压电芯上，并且还包括具有第一宽度的至少一个输入电极和具有不同于第一宽度的第二宽度的至少一个输出电极。 接地端子也在压电铁芯上。

公开(公告)号：US20140354378A1

公开(公告)日：2014-12-04

申请号：US14055707

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Jonghae KIM ,  Changhan Hobie YUN ,  Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Je-Hsiung LAN ,  Robert Paul MIKULKA ,  Matthew Michael NOWAK

IPC: H03H7/01

CPC classification number: H03H7/0138 ,  H03H7/0115 ,  Y10T29/417

Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.

Abstract translation: 滤光器包括具有通过基板通孔的玻璃基板。 滤波器还包括由玻璃基板支撑的电容器。 电容器可以具有小于打印分辨率的宽度和/或厚度。 滤波器还包括衬底内的3D电感器。 3D电感器包括耦合到贯穿衬底通孔的玻璃衬底的第一表面上的第一组迹线。 3D电感器还包括耦合到贯通衬底通孔的相对端的玻璃衬底的第二表面上的第二组迹线。 玻璃基板的第二表面与玻璃基板的第一表面相对。 直通衬底通孔和迹线作为3D电感器工作。 第一组迹线和第二组迹线也可以具有小于打印分辨率的宽度和/或厚度。

公开(公告)号：US20170372831A1

公开(公告)日：2017-12-28

申请号：US15192802

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  Daeik Daniel KIM ,  Niranjan Sunil MUDAKATTE ,  David Francis BERDY ,  Changhan Hobie YUN ,  Jonghae KIM ,  Chengjie ZUO ,  Yunfei MA ,  Robert Paul MIKULKA

IPC: H01F27/28 ,  H01F41/04 ,  H01L23/00

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F17/0033 ,  H01F2017/002 ,  H01L23/3128 ,  H01L23/645 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/023 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/1206 ,  H01L2924/18162 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.

公开(公告)号：US20170221846A1

公开(公告)日：2017-08-03

申请号：US15077869

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  Chengjie ZUO ,  David Francis BERDY ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/15 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/14 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1148 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/145 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/0052 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/09845 ,  Y02P70/611

Abstract: A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.

公开(公告)号：US20170201291A1

公开(公告)日：2017-07-13

申请号：US15151285

申请日：2016-05-10

Applicant: QUALCOMM INCORPORATED

Inventor： Shiqun GU ,  Chengjie ZUO ,  Steve FANELLI ,  Thomas GEE ,  Young Kyu SONG

IPC: H04B1/48 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L21/762 ,  H01L23/60 ,  H01L49/02 ,  H01L21/84 ,  H01L21/768 ,  H01L27/12 ,  H01L23/66

CPC classification number: H04B1/48 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/66 ,  H01L27/1203 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01L29/0649 ,  H01L2223/6672 ,  H01L2223/6677

Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.