公开(公告)号：US20160066414A1

公开(公告)日：2016-03-03

申请号：US14474860

申请日：2014-09-02

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming JOW ,  Young Kyu SONG ,  Jung Ho YOON ,  Jong-Hoon LEE ,  Xiaonan ZHANG

IPC: H05K1/02 ,  H01L23/522 ,  H05K1/18 ,  H01L21/48 ,  H05K1/11 ,  H01L49/02 ,  H01L23/528

CPC classification number: H01L23/5286 ,  H01F27/2804 ,  H01F2017/0086 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括第一体层，可包括位于第一体层上方的一个或多个电感器，耦合电感器或电感元件的变压器。 第一接地平面位于第一体层和感应元件之间的第一体层的顶部。 第一接地平面可以具有大致垂直于由感应元件产生的磁场的导线，以及与第一接地平面相对的第一体层底部的第二接地平面。 第一和第二接地平面还可以为半导体提供散热元件，以及减少或消除由电感元件产生的涡流和寄生效应。

公开(公告)号：US20160025776A1

公开(公告)日：2016-01-28

申请号：US14340387

申请日：2014-07-24

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Chang-Ho LEE

IPC: G01R1/067 ,  G01R31/28 ,  G01R1/073

CPC classification number: G01R1/06722 ,  G01R1/07314 ,  G01R31/2851

Abstract: In one aspect, a probe assembly for probing an IC is provided. The probe assembly includes a probe, which includes a probe head for contacting the integrated circuit and a body. The probe head is elongated in a first direction. The body includes a spring and an edge portion contacting the probe head. One conductor extends in a second direction and is configured to connect to a voltage potential. An electric field between the probe and the at least one conductor is perpendicular to a magnetic field of the probe. In another aspect, a probe assembly includes a first probe and second probe. Each of the first probe and the second probe is elongated in a first direction and is configured to contact an IC. A conductor extends in a second direction is provided between the first probe and the second probe. The conductor is connected to a voltage potential.

Abstract translation: 一方面，提供了用于探测IC的探针组件。 探针组件包括探针，其包括用于接触集成电路的探头和主体。 探头在第一方向上伸长。 主体包括弹簧和与探头接触的边缘部分。 一个导体沿第二方向延伸并被配置为连接到电压电位。 探针和至少一个导体之间的电场垂直于探针的磁场。 在另一方面，探针组件包括第一探针和第二探针。 第一探针和第二探针中的每一个在第一方向上是细长的并且被配置为接触IC。 在第一探针和第二探针之间设置沿第二方向延伸的导体。 导体连接到电压电位。

公开(公告)号：US20160240606A1

公开(公告)日：2016-08-18

申请号：US14625484

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming JOW ,  Young Kyu SONG ,  Jong-Hoon LEE ,  Xiaonan ZHANG

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/86 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60

Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

Abstract translation: 上平面电容器通过电介质层在下平面电容器之上隔开。 桥接后层间连接器通过第一柱和第二柱并联耦合电容。 第一柱和第二柱延伸穿过介电层，邻近上下平面电容器。 第一级耦合器延伸在介电层下方并将第一柱连接在一起并连接到下平面电容器的导体，并将下平面电容器的另一导体耦合到第二柱之一。 第二级耦合器延伸在电介质层上方，并将第二柱耦合到上平面电容器的导体，并将上平面电容器的另一导体耦合到第一柱之一。

公开(公告)号：US20160172344A1

公开(公告)日：2016-06-16

申请号：US14572753

申请日：2014-12-16

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Dong Wook KIM ,  Kyu-Pyung HWANG ,  Young Kyu SONG

IPC: H01L25/10 ,  H01L23/04 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2924/15311 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/3511

Abstract: The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity.

Abstract translation: 本公开提供了用于制造PoP半导体封装的半导体封装和方法。 PoP半导体封装可以包括第一半导体封装，第一半导体封装包括阳极氧化的金属盖结构，其包括（i）具有中心腔打开方向的中心空腔和（ii）至少一个周边空腔，其具有面向 在与中心腔打开方向相反的方向上，布置在阳极化金属盖结构的中心空腔中的第一半导体器件，电耦合到第一半导体器件的再分配层，其中形成在再分配层中的导电迹线暴露于 所述至少一个周边空腔和布置在所述至少一个周边空腔中的焊料材料以及第二半导体封装，所述第二半导体封装包括至少一个导电柱，其中所述至少一个导电柱电耦合到所述焊料材料 布置在所述至少一个周边空腔中。

公开(公告)号：US20160093571A1

公开(公告)日：2016-03-31

申请号：US14498076

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Jae Sik LEE ,  Hong Bok WE ,  Young Kyu SONG ,  Chin-Kwan KIM ,  Kyu-Pyung HWANG ,  Shiqun GU

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括在一侧具有第一再分布层的基底，在与第一再分布层相反的一侧上附接到基部的第一和第二并排裸片，附接到主动侧的插入件 以提供第一和第二管芯之间的互连，从第一和第二管芯延伸到在与第一再分布层相对的封装的表面上的第二再分配层的多个管芯通孔，以及多个 在第一和第二再分配层之间延伸穿过包装的通孔。

公开(公告)号：US20170092594A1

公开(公告)日：2017-03-30

申请号：US14865749

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Jong-Hoon LEE ,  Uei-Ming JOW

IPC: H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/065 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/37001

Abstract: Provided is a low-profile package and related techniques for use and fabrication. In an example, a low-profile package is provided. The low-profile package includes an exemplary integrated circuit (IC) having an active face, an integrated passive device (IPD) having a face, and a redistribution layer (RDL) disposed between the IPD and the IC. The IC is embedded in a substrate. The active face of the IC faces the face of the IPD in a face-to-face (F2F) configuration. At least one contact of the IPD is arranged in an overlapping configuration relative to the IC. The RDL is configured to electrically couple the IPD with the IC. The RDL can be disposed between the IPD and the IC, can be embedded in the substrate, and can be configured as an electromagnetic shield.

公开(公告)号：US20160035664A1

公开(公告)日：2016-02-04

申请号：US14450201

申请日：2014-08-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Dong Wook KIM ,  Jae Sik LEE ,  Kyu-Pyung HWANG ,  Young Kyu SONG

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L25/11

CPC classification number: H01L23/49861 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.

Abstract translation: 可以通过制造或提供具有衬底的底部封装，在衬底顶部上的至少一个管芯和衬底顶部上的焊盘来形成封装结构。 接下来，在接合焊盘上形成框架并连接到接合焊盘。 接下来，在衬底的顶部上模制封装材料以封装框架，模具和衬垫，或者基本上封装这些部件。 接下来，去除模制包装材料的一部分以暴露框架的至少一部分。 形成暴露的框架部分，使得获得所需的风扇或扇出配置。 接下来，在暴露的框架上形成非导电层。 最后，具有芯片或芯片的第二封装连接到框架的暴露部分以形成封装结构上的封装。

公开(公告)号：US20150187731A1

公开(公告)日：2015-07-02

申请号：US14141342

申请日：2013-12-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Kyu-Pyung HWANG ,  Chin-Kwan KIM ,  Young Kyu SONG ,  Hong Bok WE

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/4985 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15313

Abstract: A high-speed, high-density Input/Output bridge couples dies on a substrate to each other using a flexible connector that is attached to the substrate using solder balls disposed in openings in the substrate. Thus, the bulky, male-to-female connectors and/or silicon bridges are eliminated while still permitting dies disposed on the substrate to be coupled together.

Abstract translation: 高速，高密度输入/输出桥接器使用使用设置在基板中的开口中的焊球附接到基板的柔性连接器将基板上的管芯相互连接。 因此，消除了庞大的公对母连接器和/或硅桥，同时仍然允许设置在衬底上的管芯耦合在一起。

公开(公告)号：US20190057880A1

公开(公告)日：2019-02-21

申请号：US16168648

申请日：2018-10-23

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Kyu-Pyung HWANG ,  Hong Bok WE

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16 ,  H01G4/224 ,  H01G4/12

Abstract: Many aspects of an IC package are disclosed. The IC package includes a substrate, an integrated circuit die, a vertical capacitor and a conductive layer. The substrate includes a first plurality of substrate pads. The integrated circuit die is coupled to the first plurality of substrate pads embedded in a first layer of the substrate. The vertical capacitor has a first electrode, a second electrode and a first resistive layer. The first electrode is coupled to the first resistive layer. The first resistive layer is coupled to a first substrate pad embedded in the first layer of the substrate. The conductive layer is formed over a first surface and the second electrode of the vertical capacitor. The conductive layer encapsulates the vertical capacitor. The first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate.

公开(公告)号：US20170338179A1

公开(公告)日：2017-11-23

申请号：US15161126

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Paragkumar Ajaybhai THADESAR ,  Young Kyu SONG ,  John Jong-Hoon LEE ,  Sangjo CHOI

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/85 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/645 ,  H01L24/09 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2224/45099

Abstract: Low inductance to ground can be provided in wire-bond based device packages. An example device package may include a die on a package substrate, a mold on the package substrate and encapsulating the die, an upper ground conductor on the mold, and ground wire bonds within the mold. The die may include a plurality of terminals on an upper surface of the die. The plurality of ground wire bonds may electrically couple the die and the upper ground conductor. For each ground wire bond, a first end of that ground wire bond may be configured to electrically couple to a corresponding terminal on the upper surface of the die and a second end of that ground wire bond may be configured to electrically couple to the upper ground conductor at the upper surface of the mold.