公开(公告)号：US20180076137A1

公开(公告)日：2018-03-15

申请号：US15807169

申请日：2017-11-08

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Plamen Vassilev KOLEV ,  Michael Andrew STUBER ,  Richard HAMMOND ,  Shiqun GU ,  Steve FANELLI

IPC: H01L23/528 ,  H04B1/16 ,  H01L49/02 ,  H01L23/532 ,  H01L23/522 ,  H01L29/06 ,  H01L27/12 ,  H01L23/66

CPC classification number: H01L23/5283 ,  H01L23/5223 ,  H01L23/53209 ,  H01L23/66 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/94 ,  H01L2223/6677 ,  H04B1/16

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

公开(公告)号：US20170201291A1

公开(公告)日：2017-07-13

申请号：US15151285

申请日：2016-05-10

Applicant: QUALCOMM INCORPORATED

Inventor： Shiqun GU ,  Chengjie ZUO ,  Steve FANELLI ,  Thomas GEE ,  Young Kyu SONG

IPC: H04B1/48 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L21/762 ,  H01L23/60 ,  H01L49/02 ,  H01L21/84 ,  H01L21/768 ,  H01L27/12 ,  H01L23/66

CPC classification number: H04B1/48 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/66 ,  H01L27/1203 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01L29/0649 ,  H01L2223/6672 ,  H01L2223/6677

Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.

公开(公告)号：US20160133614A1

公开(公告)日：2016-05-12

申请号：US14536363

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Ratibor RADOJCIC ,  Mustafa BADAROGLU ,  Chunlei SHI ,  Yuancheng Christopher PAN

IPC: H01L25/16 ,  H01L23/522 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56 ,  H01L21/768 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/16 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/81005 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/00012

Abstract: The present disclosure provides semiconductor packages and methods for fabricating semiconductor packages. The semiconductor package may comprise a semiconductor device mounted to a first substrate, a voltage regulator mounted to the first substrate and coupled to the semiconductor device, and an inductive element located on a perimeter of the semiconductor device and coupled to the voltage regulator, wherein the inductive element is formed by a plurality of interconnected conductive elements extending vertically from the first substrate.

Abstract translation: 本公开提供了用于制造半导体封装的半导体封装和方法。 半导体封装可以包括安装到第一衬底的半导体器件，安装到第一衬底并耦合到半导体器件的电压调节器，以及位于半导体器件的周边并耦合到电压调节器的电感元件，其中， 电感元件由从第一基板垂直延伸的多个互连导电元件形成。

公开(公告)号：US20190259780A1

公开(公告)日：2019-08-22

申请号：US16402713

申请日：2019-05-03

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Daniel Daeik KIM ,  Matthew Michael NOWAK ,  Jonghae KIM ,  Changhan Hobie YUN ,  Je-Hsiung Jeffrey LAN ,  David Francis BERDY

IPC: H01L27/12 ,  H01L23/498 ,  H01L21/306 ,  H01L23/66 ,  H01L27/088 ,  H01L21/304 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US20160293574A1

公开(公告)日：2016-10-06

申请号：US15043484

申请日：2016-02-12

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Hong Bok WE ,  Jae Sik LEE ,  Shiqun GU

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14151 ,  H01L2224/14155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1624 ,  H01L2224/171 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/81 ,  H01L21/76898

Abstract: Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.

Abstract translation: 本公开的一些示例可以包括封装集成封装结构，其包括位于第一平面中的衬底上方的第一管芯，在第二平面中位于第一管芯上方的第二管芯，其中延伸超过第一管芯的部分， 在所述第二平面中位于所述第一模具的上方，具有延伸经过所述第一模具的部分，位于所述第二模具上方的第四模具和位于延伸通过所述第二模具和所述第三模具的部分的第三平面中的所述第三模具， 第五模具位于第二模具的上方，第三模具在第三平面中具有延伸经过第二模具和第三模具的部分。

公开(公告)号：US20160093571A1

公开(公告)日：2016-03-31

申请号：US14498076

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Jae Sik LEE ,  Hong Bok WE ,  Young Kyu SONG ,  Chin-Kwan KIM ,  Kyu-Pyung HWANG ,  Shiqun GU

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括在一侧具有第一再分布层的基底，在与第一再分布层相反的一侧上附接到基部的第一和第二并排裸片，附接到主动侧的插入件 以提供第一和第二管芯之间的互连，从第一和第二管芯延伸到在与第一再分布层相对的封装的表面上的第二再分配层的多个管芯通孔，以及多个 在第一和第二再分配层之间延伸穿过包装的通孔。

公开(公告)号：US20160013133A1

公开(公告)日：2016-01-14

申请号：US14330950

申请日：2014-07-14

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Matthew Michael NOWAK ,  Jeffrey Junhao XU

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/7682 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

Abstract translation: 系统和方法涉及包括集成电路的半导体器件，其中集成电路至少包括包含两条或更多条钨线的至少一条第一层和至少两条钨线之间的至少一个气隙，所述气隙减少 电容。 插入器耦合到集成电路，以减少两个或多个钨线和至少一个气隙的应力。 层叠封装基板可以附接到插入件，使得插入件被构造成吸收由层压封装基板和插入件之间的热膨胀系数（CTE）失配引起的机械应力，并保护气隙免受机械应力。

公开(公告)号：US20150102509A1

公开(公告)日：2015-04-16

申请号：US14578330

申请日：2014-12-19

Applicant: Qualcomm Incorporated

Inventor： Brian M. HENDERSON ,  Shiqun GU

IPC: H01L25/18 ,  H01L25/065

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/13099

Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.

Abstract translation: 半导体器件包括耦合到衬底的管芯，耦合到与衬底相对的管芯的表面的第一存储器件和耦合在与衬底相对的管芯的表面之间的耦合器件和第二存储器件 至少部分地与第一存储器件重叠。 还公开了以至少部分重叠的方式将第一和第二存储器件安装在管芯上的方法。

公开(公告)号：US20180054177A1

公开(公告)日：2018-02-22

申请号：US15240987

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil MUDAKATTE ,  David Francis BERDY ,  Changhan Hobie YUN ,  Chengjie ZUO ,  Shiqun GU ,  Mario Francisco VELEZ ,  Jonghae KIM

IPC: H03H7/01 ,  H03H1/00 ,  H03H7/46 ,  H01L49/02

CPC classification number: H03H7/0115 ,  H01L28/10 ,  H01L28/40 ,  H03H1/0007 ,  H03H7/0138 ,  H03H7/46 ,  H03H2001/0078 ,  H03H2001/0085 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09281

Abstract: A passive device may include an inductor having interconnected trace segments. The passive device may also include parallel plate capacitors. Each of the plurality of parallel plate capacitors may have a dielectric layer between a pair of conductive plates. The parallel plate capacitors may not overlap more than one of the interconnected trace segments.

公开(公告)号：US20170367594A1

公开(公告)日：2017-12-28

申请号：US15189089

申请日：2016-06-22

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  David Boettcher BAEK ,  Eugene DANTSKER

IPC: A61B5/0205 ,  A61B5/01 ,  A61B5/0488 ,  A61B5/0476 ,  A61B8/13 ,  A61B5/00 ,  A61B5/0402

CPC classification number: A61B5/02055 ,  A61B5/0059 ,  A61B5/01 ,  A61B5/02007 ,  A61B5/021 ,  A61B5/024 ,  A61B5/0402 ,  A61B5/0476 ,  A61B5/0488 ,  A61B5/053 ,  A61B5/11 ,  A61B5/6824 ,  A61B5/6831 ,  A61B5/7207 ,  A61B5/7285 ,  A61B8/13 ,  A61B2562/0219 ,  A61B2562/0247 ,  A61B2562/0271 ,  A61B2562/164

Abstract: Methods, devices, systems, and non-transitory processor-readable storage media are disclosed for determining one or more biometric properties of a subject using multiple sensors positioned along a flexible backing. At least one processor of the multi-sensor device may be configured to receive output signals from the multiple sensors, identify at least one output signal from the received output signals that exhibit measurements of a targeted biological structure, determine the one or more biometric properties of the subject based on the identified at least one output signal received from at least one of the multiple sensors, and provide the determined one or more biometric properties.