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公开(公告)号：US20130258755A1
公开(公告)日：2013-10-03
申请号：US13845503
申请日：2013-03-18
Applicant: RAMBUS, INC.
Inventor： Ravindranath Kollipara , Lei Luo , Ian Shaeffer
IPC: G11C11/401
CPC classification number: G11C11/401 , G11C5/04 , G11C7/1057 , G11C7/1084
Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.
Abstract translation: 实施例涉及具有可编程输入电容的集成电路器件。 例如，存储器件的可编程寄存器可以存储代表控制引脚的输入电容值的调整值。 一个实施例旨在通过允许较轻负载的引脚的可编程性来控制同步存储器系统的偏斜，以便增加它们的负载以匹配负载较重的引脚。 通过将较轻负载的引脚匹配到负载较重的引脚，系统表现出改进的控制和地址引脚的传播延迟同步。 此外，实施例提供了根据设备上多少等级来改变负载的能力。
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公开(公告)号：US12164808B2
公开(公告)日：2024-12-10
申请号：US17962362
申请日：2022-10-07
Applicant: Rambus Inc.
Inventor： Lei Luo , John C Eble, III
Abstract: Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes conversion circuitry to down-convert the first data at the quad data rate to the second data at the first specified data rate and up-convert the second data at the first specified data rate to the first data at the quad data rate.
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公开(公告)号：US20230112159A1
公开(公告)日：2023-04-13
申请号：US17962362
申请日：2022-10-07
Applicant: Rambus Inc.
IPC: G06F3/06
Abstract: Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes conversion circuitry to down-convert the first data at the quad data rate to the second data at the first specified data rate and up-convert the second data at the first specified data rate to the first data at the quad data rate.
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公开(公告)号：US20200349997A1
公开(公告)日：2020-11-05
申请号：US16865928
申请日：2020-05-04
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lei Luo , Liji Gopalakrishnan
IPC: G11C11/4076 , G11C11/4096 , G11C7/10 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/4074 , G06F1/3237 , G06F1/04 , G06F1/3234 , G06F1/08 , G11C11/408
Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
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公开(公告)号：US10268252B2
公开(公告)日：2019-04-23
申请号：US15863712
申请日：2018-01-05
Applicant: Rambus Inc.
Inventor： Yu Chang , Lei Luo , Kyung Suk Oh
Abstract: Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.
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Patent Agency Ranking
公开(公告)号：US20190043551A1
公开(公告)日：2019-02-07
申请号：US16032633
申请日：2018-07-11
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lei Luo , Liji Gopalakrishnan
IPC: G11C11/4076 , G11C11/4096 , G11C7/22 , G06F1/04 , G11C7/10 , G06F1/32 , G11C11/408 , G11C11/4072 , G11C11/4074 , G06F1/08 , G11C7/20
CPC classification number: G11C11/4076 , G06F1/04 , G06F1/08 , G06F1/3234 , G06F1/3237 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/4074 , G11C11/4087 , G11C11/4096 , Y02D10/128 , Y02D50/20
Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
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公开(公告)号：US10067519B2
公开(公告)日：2018-09-04
申请号：US15626096
申请日：2017-06-17
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
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公开(公告)号：US20180083642A1
公开(公告)日：2018-03-22
申请号：US15667184
申请日：2017-08-02
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
CPC classification number: H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03K5/1565 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
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公开(公告)号：US09870040B2
公开(公告)日：2018-01-16
申请号：US15012681
申请日：2016-02-01
Applicant: Rambus Inc.
Inventor： Yu Chang , Lei Luo , Kyung Suk Oh
CPC classification number: G06F1/3203 , H04B1/12 , H04L7/0054 , H04L7/033 , H04L25/03006 , H04L25/03012 , H04L25/03057 , H04L25/03127 , H04L25/03146 , H04L25/03853 , H04L2025/03433
Abstract: Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.
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公开(公告)号：US20170323672A1
公开(公告)日：2017-11-09
申请号：US15604251
申请日：2017-05-24
Applicant: Rambus Inc.
Inventor： Ian P. Shaeffer , Lei Luo
CPC classification number: G11C7/22 , G06F1/08 , G06F13/16 , G06F13/4068 , G06F13/4243 , G11C7/1072
Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.
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