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43 条记录 (耗时 0.022 秒)

    MCM—MLC technology
    33.
    发明授权
    MCM—MLC technology 失效
    MCM-MLC技术

    公开(公告)号：US06442041B2

    公开(公告)日：2002-08-27

    申请号：US09740280

    申请日：2000-12-19

    申请人： Simone Rehm ,  Bernd Garden ,  Erich Klink ,  Gisbert Thomke ,  William F. Shutler

    发明人： Simone Rehm ,  Bernd Garden ,  Erich Klink ,  Gisbert Thomke ,  William F. Shutler

    IPC分类号： H05K702

    CPC分类号： H05K1/0224 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/0289 ,  H05K1/0298 ,  H05K2201/09681 ,  H01L2924/00

    摘要： Disclosed is a multilayer electronics packaging structure, especially for use in a multi chip module. By forming an overlap of signal conductors by the respective mesh conductors, an improved shielding effect is achieved and coupling between signal conductors is reduced. By increasing the via punch pitch such that multiple wiring channels are formed between adjacent vias, wirability is improved and the number of signal distribution layers may be reduced. The new structure thus shows improved electrical properties over the state-of-the-art structures, combined with a cost reduction of about 35%.

    摘要翻译： 公开了一种多层电子封装结构，特别适用于多芯片模块。 通过由相应的网状导体形成信号导体的重叠，实现了改进的屏蔽效果，并且减少了信号导线之间的耦合。 通过增加通孔冲压间距，使得在相邻通路之间形成多个布线通道，可改善布线性，并且可以减少信号分布层的数量。 因此，新结构显示出比现有技术结构更好的电性能，同时成本降低约35％。

    Input signal redriver for semiconductor modules
    34.
    发明授权
    Input signal redriver for semiconductor modules 失效
    用于半导体模块的输入信号转接器

    公开(公告)号：US5157635A

    公开(公告)日：1992-10-20

    申请号：US728831

    申请日：1991-07-09

    申请人： Wayne F. Ellis ,  Erich Klink ,  Knut Najmann

    发明人： Wayne F. Ellis ,  Erich Klink ,  Knut Najmann

    IPC分类号： G11C7/22 ,  G11C8/18

    CPC分类号： G11C8/18 ,  G11C7/22

    摘要： A semiconductor packaging subassembly is described in which a plurality of modules or chips, repsonsive to a plurality of common input signals, are provided with input signal redriver circuits. Each redriver circuit is responsive to an input and provides an output signal to each the of chips in the subassembly. The preferred embodiment is directed to a multi-module memory arrangement in which input signals including CAS, RAS, W and address signals are received and redriven.

    摘要翻译： 描述了一种半导体封装子组件，其中对多个公共输入信号重现的多个模块或芯片设置有输入信号转接电路。 每个转接电路响应于输入，并向子组件中的每个芯片提供输出信号。 优选实施例涉及一种多模块存储装置，其中包括CAS，RAS，W和地址信号的输入信号被接收并重新驱动。

    Integrated circuit package
    37.
    发明授权
    Integrated circuit package 失效
    集成电路封装

    公开(公告)号：US5162264A

    公开(公告)日：1992-11-10

    申请号：US696675

    申请日：1991-05-07

    申请人： Werner O. Haug ,  Erich Klink ,  Karl E. Kroll ,  Thomas Ludwig ,  Helmut Schettler ,  Rainer Stahl ,  Otto M. Wagner

    发明人： Werner O. Haug ,  Erich Klink ,  Karl E. Kroll ,  Thomas Ludwig ,  Helmut Schettler ,  Rainer Stahl ,  Otto M. Wagner

    IPC分类号： H01L21/60 ,  H01L23/14 ,  H01L23/64

    CPC分类号： H01L23/642 ,  H01L23/147 ,  H01L2224/16 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/3011 ,  Y10S257/916 ,  Y10S438/901

    摘要： Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

    摘要翻译： 集成电路封装，包括电源分配布线和芯片互连信号布线，两者均形成在其中实现电源去耦电容器的无源半导体互连载体（2）的顶表面上。 在第二导电类型的所述载体的表面中提供第一导电类型的间隔阱（4）。 电源分配布线包括在第一布线层（WL1）内的第一和第二导线（5,6）。 所述第一导线（5）以欧姆接触关系沉积在所述阱（4）的表面区域上，并且所述第二导线（6）沉积在所述孔（4）之间的所述载体（2）的表面区域上， 在欧洲的联系关系。 所述第一和第二导线分别连接到电源的第一和第二端子，使得所述阱（4）和嵌入所述阱的载体材料（2）之间的结电容形成所述去耦电容器。 至少一个有源集成电路芯片（1）被安装并电连接到无源半导体互连载体（2）。

    Phase splitter with latch
    38.
    发明授权
    Phase splitter with latch 失效
    相分离器带闩锁

    公开(公告)号：US4614885A

    公开(公告)日：1986-09-30

    申请号：US630544

    申请日：1984-07-13

    申请人： Rudolf Brosch ,  Joachim Keinert ,  Erich Klink ,  Friedrich C. Wernicke

    发明人： Rudolf Brosch ,  Joachim Keinert ,  Erich Klink ,  Friedrich C. Wernicke

    IPC分类号： H03K3/286 ,  H03K3/288 ,  H03K5/02 ,  H03K5/151 ,  H03K3/023

    CPC分类号： H03K3/288

    摘要： A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transistor (T11). Upon actuation of the output stage, i.e., when transistor (T11) is on, the active emitter resistance of one of the cross-coupled transistors (T6, T7) is pulled below the value of the emitter resistors (R6, R7) of the emitter followers (T4, T5), thus causing the latch circuit to be latched as a function of the input signal.

    摘要翻译： 具有锁存器的分相器包括形式为电流开关（T1，T2，T3，R3）形式的真互补发生器，其根据输入信号（VIN）提供两个互补输出信号。 这种真互补发生器的输出在每种情况下都连接到相关的射极跟随器（T4，T5）。 两个发射极跟随器（T4，T5）具有相同的发射极电阻（R6，R7），其同时用作两个交叉耦合晶体管（T6，T7）的集电极负载电阻，其也包括相同但较高的发射极电阻（R13，R14） 发射极跟随器（T6，T7）。 交叉耦合晶体管（T6，T7）的发射极各自连接到由电流开关组成的输出级（T8，T9，T11）的两个输入之一。 该电流开关通过时钟控制的过渡器（T11）连接到工作电压（VEE）。 在激励输出级时，即当晶体管（T11）导通时，其中一个交叉耦合晶体管（T6，T7）的有源发射极电阻被拉低到低于发射极电阻（R6，R7）的值 发射极跟随器（T4，T5），从而使闩锁电路根据输入信号被锁存。

    Phase splitter with integrated latch circuit
    39.
    发明授权
    Phase splitter with integrated latch circuit 失效
    具有集成锁存电路的分相器

    公开(公告)号：US4542309A

    公开(公告)日：1985-09-17

    申请号：US468447

    申请日：1983-02-22

    申请人： Wilfried Klein ,  Erich Klink ,  Knut Najmann ,  Friedrich Wernicke

    发明人： Wilfried Klein ,  Erich Klink ,  Knut Najmann ,  Friedrich Wernicke

    IPC分类号： H03K3/286 ,  H03K3/287 ,  H03K19/20 ,  H03K5/22 ,  H03K17/56

    CPC分类号： H03K3/287

    摘要： Disclosed is a phase splitter with integrated latch circuit, where the complementary output signals generated after an input signal applied to a true-complement generator are available directly without any load by the latch circuit, where upon a premature change of the input signal there is no undesired change of the previously set switching state or of the output signals, respectively, and where a simple clocking for functional control can be used. The advantages presented by the disclosed Phase splitter substantially consist in that the speed with which the complementary output signals are supplied is extremely high since the output signals are available directly, i.e. with only one stage delay, the latch circuit being non-conductive in the stationary state, and thus in a latching process does not have to be switched from one stage to the other, but only switched on.

    摘要翻译： 公开了一种具有集成锁存电路的分相器，其中在输入信号施加到真互补发生器之后产生的互补输出信号可直接获得，而锁存电路不需要任何负载，其中当输入信号的过早变化 分别预先设定的开关状态或输出信号的不期望的变化，以及可以使用用于功能控制的简单时钟。 所公开的相位分离器所呈现的优点基本上在于，互补输出信号的供给速度非常高，因为输出信号可以直接获得，即只有一级延迟，锁存电路在静态中是不导通的 状态，因此在锁定过程中不必从一个阶段切换到另一个阶段，而是仅被接通。