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公开(公告)号：US20160205773A1
公开(公告)日：2016-07-14
申请号：US15074209
申请日：2016-03-18
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Doo Hwan LEE , Yul Kyo CHUNG , Yee Na SHIN , Seung Eun LEE
CPC classification number: H05K3/002 , H01L24/19 , H01L24/24 , H01L24/82 , H01L2224/12105 , H01L2224/24227 , H01L2224/73267 , H01L2224/92244 , H01L2924/12042 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/3511 , H05K1/0271 , H05K1/0298 , H05K1/0306 , H05K1/115 , H05K1/185 , H05K3/4605 , H05K3/4644 , H05K3/4697 , H05K2201/10015 , H05K2203/1469 , Y10T29/4913 , H01L2924/00
Abstract: A circuit board includes an inorganic material insulating layer, a first circuit pattern layer formed on a surface of the inorganic material insulating layer, a first build-up insulating layer formed on the inorganic material insulating layer and formed of an organic material, and a second circuit pattern layer formed on a surface of the first build-up insulating layer.
Abstract translation: 电路板包括无机材料绝缘层，形成在无机材料绝缘层的表面上的第一电路图案层，形成在无机材料绝缘层上并由有机材料形成的第一累积绝缘层，第二 电路图案层形成在第一堆积绝缘层的表面上。
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公开(公告)号：US20160105956A1
公开(公告)日：2016-04-14
申请号：US14877291
申请日：2015-10-07
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Jun Oh HWANG , Kwang Hee KWON , Seung Eun LEE , Young Kwan LEE , Yul Kyo CHUNG , Se Rang IM , Ki Jung SUNG
CPC classification number: H05K3/205 , H05K1/115 , H05K3/108 , H05K2203/054
Abstract: The present invention provides a printed circuit board includes an insulating member, a first plating layer buried in a bottom region of the insulating member, a second plating layer buried in a top region of the insulating member and a plating via for electrically connecting the first plating layer and the second plating layer by being buried in any one among the top region and the bottom region of the insulating member.
Abstract translation: 本发明提供了一种印刷电路板，包括绝缘构件，埋在绝缘构件的底部区域中的第一镀层，埋在绝缘构件的顶部区域中的第二镀层，以及用于将第一镀层 层和第二镀层被埋在绝缘构件的顶部区域和底部区域中的任一个中。
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公开(公告)号：US20150366059A1
公开(公告)日：2015-12-17
申请号：US14731366
申请日：2015-06-04
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Seung Eun LEE , Myung Sam KANG , Kwang Hee KWON , Seung Yeop KOOK , Se Rang IM
CPC classification number: H05K1/111 , H05K3/108 , H05K3/4007 , H05K2203/054 , H05K2203/1461 , Y02P70/611 , Y10T29/49156
Abstract: A seed layer and a resist layer are formed on a solder resist layer, and the resist layer is patterned to form connection pads and pad plating layers. Then, the resist layer is removed, and the seed layer exposed to the outside is removed. A device may be mounted on this circuit board, and a connection terminal of the device and the connection pad of the circuit board may be connected to each other by a wire, or the like.
Abstract translation: 在阻焊层上形成种子层和抗蚀剂层，对抗蚀剂层进行图案化以形成连接焊盘和焊盘镀层。 然后，去除抗蚀剂层，并且去除暴露于外部的种子层。 设备可以安装在该电路板上，并且电路板的连接端子和电路板的连接焊盘可以通过导线等相互连接。
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公开(公告)号：US20150364539A1
公开(公告)日：2015-12-17
申请号：US14585183
申请日：2014-12-30
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Se Rang IM , Seung Eun LEE , Seung Yeop KOOK , Myung Sam KANG
IPC: H01L49/02 , H01L23/498
CPC classification number: H01L23/49827 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L25/16 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H05K1/162 , H05K3/4682 , H05K2201/10159 , H01L2924/00014 , H01L2924/00
Abstract: There are provided a package board and a package using the same. The package board according to an exemplary embodiment of the present disclosure includes: an insulating layer; a dielectric layer formed on the insulating layer; a lower electrode formed on a whole surface of an upper surface of the insulating layer; and an upper electrode formed on a whole surface of an upper surface of the dielectric layer.
Abstract translation: 提供了一个包装板和一个使用它的包装。 根据本公开的示例性实施例的封装板包括：绝缘层; 形成在所述绝缘层上的电介质层; 形成在所述绝缘层的上表面的整个表面上的下电极; 以及形成在电介质层的上表面的整个表面上的上电极。
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Patent Agency Ranking
35.发明申请PACKAGE SUBSTRATE, PACKAGE, PACKAGE ON PACKAGE AND MANUFACTURING METHOD OF PACKAGE SUBSTRATE 审中-公开包装衬底，包装，包装和包装衬底的制造方法公开(公告)号：US20150348918A1
公开(公告)日：2015-12-03
申请号：US14597777
申请日：2015-01-15
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Jin Seon PARK , Seung Eun LEE , Mi Ja HAN , Seung Yeop KOOK , Je Gwang YOO , Ju Hee PARK , Jong Rip KIM , Myung Sam KANG
IPC: H01L23/64 , H01L21/50 , H01L25/065 , H01L23/00 , H01L23/498
CPC classification number: H01L23/642 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L24/48 , H01L25/105 , H01L2224/16227 , H01L2224/32225 , H01L2224/32238 , H01L2224/48091 , H01L2224/48237 , H01L2225/1023 , H01L2924/00014 , H01L2924/15311 , H01L2924/15313 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
Abstract: A package substrate, a package, a package on package, and a manufacturing method of a package substrate. A package substrate according to one exemplary embodiment includes: an insulating layer; a circuit layer formed on the insulating layer; and a capacitor including a lower electrode, an upper electrode, and a dielectric layer formed between the lower electrode and the upper electrode, the lower electrode and the dielectric layer being buried in the insulating layer and the upper electrode being formed on an upper portion of the insulating layer.
Abstract translation: 封装基板，封装，封装上的封装以及封装基板的制造方法。 根据一个示例性实施例的封装基板包括：绝缘层; 形成在所述绝缘层上的电路层; 以及电容器，包括形成在下电极和上电极之间的下电极，上电极和电介质层，下电极和电介质层被埋在绝缘层中，上电极形成在上电极的上部 绝缘层。
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36.发明申请PACKAGE BOARD, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE USING THE SAME 审中-公开包装板及其制造方法和使用其的半导体封装公开(公告)号：US20150195905A1
公开(公告)日：2015-07-09
申请号：US14457109
申请日：2014-08-11
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Myung Sam KANG , Seung Eun LEE , Seung Yeop KOOK , Ki Jung SUNG , Ju Hee PARK , Je Gwang YOO , Jin Seon PARK
CPC classification number: H05K3/4644 , H01G4/33 , H01L21/6835 , H01L23/145 , H01L23/3121 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L23/642 , H01L2221/68345 , H01L2224/32112 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H01L2924/15313 , H01L2924/181 , H05K1/115 , H05K1/162 , H05K3/284 , H05K2201/10159 , H05K2203/1453 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: There are provided a package board, a method of manufacturing the same, and a semiconductor package using the same. According to an exemplary embodiment of the present disclosure, the package substrate may include: an insulating layer; a circuit layer formed on and beneath the insulating layer; a capacitor formed in the insulating layer and including an upper electrode, a lower electrode, and a dielectric layer formed between the upper electrode and the lower electrode; and a via connecting the circuit layer to the upper electrode and the lower electrode.
Abstract translation: 提供了一种封装板，其制造方法和使用该封装板的半导体封装。 根据本公开的示例性实施例，封装基板可以包括：绝缘层; 在绝缘层上形成的电路层; 形成在所述绝缘层中并且包括形成在所述上电极和所述下电极之间的上电极，下电极和电介质层的电容器; 以及将电路层连接到上电极和下电极的通孔。
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公开(公告)号：US20140182916A1
公开(公告)日：2014-07-03
申请号：US14064951
申请日：2013-10-28
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Yee Na SHIN , Seung Eun LEE , Yul Kyo CHUNG , Doo Hwan LEE
CPC classification number: H05K1/115 , H01L2224/04105 , H01L2224/2518 , H05K1/185 , H05K3/421 , H05K3/4602 , H05K2201/0195 , H05K2201/09481 , H05K2201/09509 , H05K2201/09563 , H05K2201/09854 , H05K2201/10636 , H05K2203/1469 , Y02P70/611 , Y10T29/49139
Abstract: The present invention relates to a circuit board, which can miniaturize a conductor pattern formed around a via and improve current pass characteristics of the via at the same time by including a via passing through an insulating layer to be in contact with an upper conductor pattern and a lower conductor pattern and having a bent portion whose cross-sectional area or diameter changes discontinuously.
Abstract translation: 电路板本发明涉及一种电路板，其可以使形成在通孔周围的导体图案小型化，同时通过包括与上导体图案接触的绝缘层的通孔，同时改善通孔的电流通过特性， 下导体图案并具有弯曲部分，其横截面积或直径不连续地变化。
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公开(公告)号：US20140182897A1
公开(公告)日：2014-07-03
申请号：US14143682
申请日：2013-12-30
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Doo Hwan LEE , Yul Kyo CHUNG , Yee Na SHIN , Seung Eun LEE
CPC classification number: H05K3/002 , H01L24/19 , H01L24/24 , H01L24/82 , H01L2224/12105 , H01L2224/24227 , H01L2224/73267 , H01L2224/92244 , H01L2924/12042 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/3511 , H05K1/0271 , H05K1/0298 , H05K1/0306 , H05K1/115 , H05K1/185 , H05K3/4605 , H05K3/4644 , H05K3/4697 , H05K2201/10015 , H05K2203/1469 , Y10T29/4913 , H01L2924/00
Abstract: A circuit board includes an inorganic material insulating layer, a first circuit pattern layer formed on a surface of the inorganic material insulating layer, a first build-up insulating layer formed on the inorganic material insulating layer and formed of an organic material, and a second circuit pattern layer formed on a surface of the first build-up insulating layer.
Abstract translation: 电路板包括无机材料绝缘层，形成在无机材料绝缘层的表面上的第一电路图案层，形成在无机材料绝缘层上并由有机材料形成的第一累积绝缘层，第二 电路图案层形成在第一堆积绝缘层的表面上。
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公开(公告)号：US20140182895A1
公开(公告)日：2014-07-03
申请号：US14143527
申请日：2013-12-30
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Doo Hwan LEE , Ho Shik KANG , Yee Na SHIN , Yul Kyo CHUNG , Seung Eun LEE
CPC classification number: H05K1/0271 , H01L21/568 , H01L24/18 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/15311 , H01L2924/3511 , H05K1/185 , H05K3/0097 , H05K3/4682 , H05K3/4688 , H05K2201/0175 , H05K2201/068 , H05K2203/0152 , H05K2203/1572 , Y10T29/4913 , Y10T29/49155 , H01L2224/83005
Abstract: A multilayered substrate and a method of manufacturing the same. The multilayered substrate includes a plurality of wiring layers and reinforcing layers disposed at the outermost portions of both surfaces of the multilayered substrate, respectively, in order to decrease warpage of the multilayered substrate and has wiring patterns optimized depending on a scheme in which external electrodes are formed on an electronic component.
Abstract translation: 一种多层基板及其制造方法。 多层基板包括分别设置在多层基板的两个表面的最外部的多个布线层和加强层，以减少多层基板的翘曲，并且具有根据外部电极为 形成在电子元件上。
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