公开(公告)号：US11728230B2

公开(公告)日：2023-08-15

申请号：US17350329

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Dongho Kim ,  Jin-Woo Park ,  Jongbo Shim

IPC: H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/13 ,  H01L21/4853 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/1023 ,  H01L2225/1058

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate, wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

公开(公告)号：US11715645B2

公开(公告)日：2023-08-01

申请号：US17656695

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Park ,  Jin-Woo Park ,  Seok Hyun Lee ,  Jae Gwon Jang ,  Gwang Jae Jeon

IPC: H01L21/48 ,  H01L21/52 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L21/52 ,  H01L21/565 ,  H01L23/49816 ,  H01L25/50

Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

公开(公告)号：US09768537B2

公开(公告)日：2017-09-19

申请号：US15084901

申请日：2016-03-30

Applicant: Samsung Electronics Co., Ltd. ,  HYUPJINCONNECTOR Co., Ltd.

Inventor： Kyung-Jong Kim ,  Seung-Kyo Hong ,  Yang-Jean Park ,  Jin-Woo Park

IPC: H01R12/00 ,  H01R12/71 ,  H01R12/70 ,  H01R13/24

CPC classification number: H01R12/714 ,  H01R12/7076 ,  H01R12/718 ,  H01R13/2464

Abstract: A connecting terminal device may include: a bottom plate; a movable part provided on a rear surface of the bottom plate that is configured to be electrically connected to an external object as the movable part is pressed or raised; one or more protective walls provided on side surfaces of the bottom plate; pressing preventing parts provided at ends of the protective walls and provided between the bottom plate and the movable plate to restrict a pressing movement of the movable part; and rising preventing parts provided on side surfaces of the protective walls to restrict a rising movement of the movable part.

公开(公告)号：US09425111B2

公开(公告)日：2016-08-23

申请号：US14751626

申请日：2015-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Ji Hwang Kim ,  Jongbo Shim

IPC: H01L23/48 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/49816 ,  H01L25/065 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pad including a connection pad and a measurement pad; and a chip bump including a first bump provided between the package substrate and the connection pad and a second bump provided between the package substrate and the measurement pad. An interconnection disposed within the package substrate is not connected to the second bump to be electrically isolated from the second bump.

Abstract translation: 半导体封装包括封装衬底; 安装在所述封装衬底的顶表面上的半导体芯片; 芯片焊盘，其设置在所述半导体芯片的底面上以面向所述封装基板的上表面，所述芯片焊盘包括连接焊盘和测量焊盘; 以及包括设置在封装基板和连接焊盘之间的第一凸起的芯片凸块和设置在封装基板和测量垫之间的第二凸块。 设置在封装基板内的互连件不与第二凸块连接以与第二凸块电隔离。

公开(公告)号：US09224710B2

公开(公告)日：2015-12-29

申请号：US14463854

申请日：2014-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Woo Park

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/49 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/20757 ,  H01L2924/20756 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2224/05599 ,  H01L2924/014

Abstract: Provided is a semiconductor package, the semiconductor package includes a first substrate, a first semiconductor chip which is mounted on the first substrate, a second substrate which is disposed on the first semiconductor chip, at least one second semiconductor chip which is disposed on the second substrate; and a plurality of wires which are in contact with the first substrate and the second substrate to connect the first substrate and the second substrate to each other.

Abstract translation: 提供一种半导体封装，该半导体封装包括第一衬底，安装在第一衬底上的第一半导体芯片，设置在第一半导体芯片上的第二衬底，设置在第二衬底上的至少一个第二半导体芯片 基质; 以及与第一基板和第二基板接触以将第一基板和第二基板彼此连接的多根电线。

公开(公告)号：US09093439B2

公开(公告)日：2015-07-28

申请号：US13944224

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hyun Lee ,  Jin-Woo Park

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

Abstract: According to example embodiments, a semiconductor package includes: a lower molding element; a lower semiconductor chip in the lower molding element and having lower chip pads on an upper surface and at an areas close to first and second sides of the lower molding element; conductive pillars surrounding the lower semiconductor chip and passing through the lower molding element; an upper semiconductor chip on the upper surface of the lower molding element and lower semiconductor chip, the upper semiconductor chip having upper chip pads on a top surface and at areas close to third and the fourth sides of the upper semiconductor chip, and a connecting structure on the lower molding element and the upper semiconductor chip and electrically connecting each of the lower chip pads and upper chip pads to a corresponding conductive pillar. The upper semiconductor chip is substantially orthogonal to the lower semiconductor chip.

Abstract translation: 根据示例性实施例，半导体封装包括：下模制元件; 下部模制元件中的下部半导体芯片，并且在上表面和靠近下部模制元件的第一和第二侧的区域中具有下部芯片焊盘; 导电柱围绕下半导体芯片并通过下模制元件; 在下模塑元件的上表面上的上半导体芯片和下半导体芯片，上半导体芯片在顶表面上具有上芯片焊盘，并且在上半导体芯片的靠近第三和第四侧的区域处具有连接结构 在下模制元件和上半导体芯片上，并且将每个下芯片焊盘和上芯片焊盘电连接到相应的导电柱。 上半导体芯片基本上正交于下半导体芯片。

公开(公告)号：US08890333B2

公开(公告)日：2014-11-18

申请号：US13886758

申请日：2013-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeokHyun Lee ,  Jin-Woo Park ,  Taesung Park

IPC: H01L29/40

CPC classification number: H01L21/76892 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76822 ,  H01L21/76894 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/82365 ,  H01L2224/95 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/01029 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract translation: 堆叠的半导体芯片包括将半导体芯片电连接到每个芯片的无接线的互连。 在半导体芯片之间的粘合层中的开口可以提供用于从沿着半导体芯片的侧壁绝缘层的一个半导体芯片上的接合焊盘沿另一个半导体芯片的侧壁绝缘层到接合焊盘的互连的路径 另一个半导体芯片。