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    METALLIC CARRIER FOR LAYER TRANSFER AND METHODS FOR FORMING THE SAME
    31.
    发明申请
    METALLIC CARRIER FOR LAYER TRANSFER AND METHODS FOR FORMING THE SAME 审中-公开
    用于层传送的金属载体及其形成方法

    公开(公告)号：US20130221496A1

    公开(公告)日：2013-08-29

    申请号：US13848201

    申请日：2013-03-21

    Applicant: Soitec

    Inventor： Christiaan J. Werkhoven ,  Chantal Arena

    IPC: H01L21/762 ,  H01L29/02

    CPC classification number: H01L21/76256 ,  H01L21/187 ,  H01L29/02 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/40 ,  H01L2933/0016

    Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer.

    Abstract translation: 实施例涉及半导体结构及其形成方法。 在一些实施例中，所述方法可用于通过在预定深度处在供体结构中形成弱化区以制造半导体衬底，以在附着表面和弱化区之间限定转移层，以及在弱化区和弱化区之间的残留施主结构 与附接表面相对的表面。 在附着表面上形成金属层，并且在金属层和转移层之间提供欧姆接触，匹配的金属层的热膨胀系数（CTE）与转印层的CTE紧密匹配，并具有足够的刚度 为转移层提供结构支持。 在弱化区将转移层与供体结构分离，以形成包含转移层金属层的复合衬底。

    THERMALIZATION OF GASEOUS PRECURSORS IN CVD REACTORS
    32.
    发明申请
    THERMALIZATION OF GASEOUS PRECURSORS IN CVD REACTORS 有权
    CVD反应器中气相前体的热化

    公开(公告)号：US20130137247A1

    公开(公告)日：2013-05-30

    申请号：US13751558

    申请日：2013-01-28

    Applicant: Soitec

    Inventor： Chantal Arena ,  Christiaan J. Werkhoven ,  Ronald Thomas Bertram, JR. ,  Ed Lindow

    IPC: H01L21/02

    CPC classification number: H01L21/0262 ,  C23C16/303 ,  C23C16/448 ,  C30B25/105

    Abstract: The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.

    Abstract translation: 本发明涉及半导体处理领域，并且提供了通过在其反应之前促进前体气体的更有效的热化来改善半导体材料的化学气相沉积（CVD）的方法。 在优选的实施方案中，该方法提供热传递结构及其在CVD反应器内的布置，以便促进对流动的工艺气体的热传递。 在适用于对来自加热灯的辐射透明的CVD反应器的某些优选实施方案中，本发明提供放射吸收表面，其被放置以拦截来自加热灯的辐射并将其转移到流动的工艺气体。

    Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters
    33.
    发明授权
    Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters 有权

    公开(公告)号：US09793360B2

    公开(公告)日：2017-10-17

    申请号：US14314804

    申请日：2014-06-25

    Applicant: Soitec

    Inventor： Chantal Arena

    IPC: H01L29/20 ,  H01L21/18 ,  H01L21/762 ,  H01L33/00

    CPC classification number: H01L29/2003 ,  H01L21/187 ,  H01L21/76254 ,  H01L33/0079

    Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

    Gallium trichloride injection scheme
    34.
    发明授权
    Gallium trichloride injection scheme 有权
    三氯化镓注射方案

    公开(公告)号：US09481943B2

    公开(公告)日：2016-11-01

    申请号：US13680241

    申请日：2012-11-19

    Applicant: Soitec

    Inventor： Chantal Arena ,  Christiaan Werkhoven

    IPC: C23C16/30 ,  C23C16/44 ,  C23C16/455 ,  C30B25/10 ,  C30B29/40 ,  C30B35/00 ,  H01L21/02 ,  C30B25/14

    CPC classification number: C30B25/10 ,  C23C16/303 ,  C23C16/4411 ,  C23C16/4412 ,  C23C16/45504 ,  C23C16/45593 ,  C30B25/14 ,  C30B29/406 ,  C30B35/00 ,  H01L21/0254 ,  H01L21/0262

    Abstract: A system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The system includes sources of the reactants, one of which is a gaseous Group III precursor having one or more gaseous gallium precursors and another of which is a gaseous Group V component, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their monomer forms.

    Abstract translation: 一种用于外延沉积包括镓的III-V族III族半导体材料的系统。 该系统包括反应物的源，其中之一是具有一种或多种气态镓前体的气态III族前体，另一种是气态V族组分，其中反应物结合沉积III-V族半导体材料 以及一个或多个加热结构，用于在反应温度之前加热气态III族前体，以将这些前体的基本上所有的二聚体，三聚体或其它分子变体分解为它们的单体形式。

    Abatement of reaction gases from gallium nitride deposition
    37.
    发明授权
    Abatement of reaction gases from gallium nitride deposition 有权
    减少氮化镓沉积反应气体

    公开(公告)号：US09038565B2

    公开(公告)日：2015-05-26

    申请号：US14055281

    申请日：2013-10-16

    Applicant: Soitec

    Inventor： Chantal Arena ,  Christiaan Werkhoven

    IPC: B05C11/00 ,  C23C16/00 ,  C30B25/14 ,  C23C16/44 ,  C30B29/40 ,  C30B25/08 ,  C30B25/16

    CPC classification number: C30B25/14 ,  C23C16/4412 ,  C30B25/08 ,  C30B25/165 ,  C30B29/40 ,  C30B29/403

    Abstract: Systems for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment is optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material.

    Abstract translation: 用于持续，大批量生产适用于制造光学和电子部件的III-V族化合物半导体材料的系统，用作外延沉积的基板或晶片。 该设备被优化用于生产III-N（氮）化合物半导体晶片，并专门用于生产GaN晶片。 该方法包括将一定量的作为一种反应物的气态III族前体与一定量的气态V族组分作为反应室中的另一反应物反应以形成半导体材料; 去除废气，包括未反应的III族前体，未反应的V族组分和反应副产物; 并将废气加热到足以减少其冷凝的温度，并且增强半导体材料的制造。 有利地，排气被加热以充分避免冷凝，以促进半导体材料的持续高容量制造。

    MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES
    38.
    发明申请
    MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES 审中-公开
    多功能太阳能电池器件的制造

    公开(公告)号：US20150083202A1

    公开(公告)日：2015-03-26

    申请号：US14386952

    申请日：2013-03-03

    Applicant: Soitec

    Inventor： Bruno Ghyselen ,  Chantal Arena ,  Frank Dimroth ,  Andreas W. Bett

    IPC: H01L31/0725 ,  H01L31/18

    CPC classification number: H01L31/0725 ,  C30B29/06 ,  C30B33/06 ,  H01L31/03046 ,  H01L31/0687 ,  H01L31/1844 ,  H01L31/1852 ,  H01L31/1864 ,  Y02E10/544 ,  Y02P70/521

    Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first engineered substrate; providing a second substrate; forming at least one first solar cell layer on the first engineered substrate to obtain a first wafer structure; forming at least one second solar cell layer on the second substrate to obtain a second wafer structure; bonding the first wafer structure to the second wafer structure; detaching the first engineered substrate; removing the second substrate; and bonding a third substrate to the at least one first solar cell layer.

    Abstract translation: 本发明涉及一种用于制造多结太阳能电池器件的方法，包括以下步骤：提供第一工程衬底; 提供第二基板; 在所述第一工程衬底上形成至少一个第一太阳能电池层以获得第一晶片结构; 在所述第二基板上形成至少一个第二太阳能电池层以获得第二晶片结构; 将所述第一晶片结构接合到所述第二晶片结构; 拆卸第一工程衬底; 去除所述第二基板; 以及将第三衬底接合到所述至少一个第一太阳能电池层。

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