System and method for performing memory operations in a computing system
    31.
    发明授权
    System and method for performing memory operations in a computing system 有权
    用于在计算系统中执行存储器操作的系统和方法

    公开(公告)号:US07398359B1

    公开(公告)日:2008-07-08

    申请号:US10836932

    申请日:2004-04-30

    IPC分类号: G06F12/00

    摘要: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

    摘要翻译: 处理器可以以多个操作状态中的一个操作。 在正常操作状态下,处理器不涉及存储器事务。 在接收到访问存储器位置的事务指令时,处理器转换到事务操作状态。 在事务操作状态下,处理器执行对高速缓存行的更改和与存储器位置相关联的数据。 在事务操作状态下,数据和高速缓存行的任何更改对于计算系统中的其他处理器是不可见的。 响应于接收到提交指令,处理器进入提交操作状态时,这些更改变得可见。 更改变为可见后,处理器返回到正常运行状态。 如果在接收提交指令之前发生中止事件,则处理器转换到中止操作状态,其中对数据和高速缓存行的任何改变被丢弃。

    Method and system for managing data at an input/output interface for a multiprocessor system
    32.
    发明授权
    Method and system for managing data at an input/output interface for a multiprocessor system 有权
    用于在多处理器系统的输入/输出接口处管理数据的方法和系统

    公开(公告)号:US06859863B1

    公开(公告)日:2005-02-22

    申请号:US09910631

    申请日:2001-07-20

    IPC分类号: G06F12/08 G06F12/14 G06F12/00

    摘要: A multiprocessor system and method includes a processing sub-system including a plurality of processors and a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store a copy of data from the processor memory system for use by a corresponding peripheral device and to delete the copy at a first time event. A directory for the processor is operable to identify the data as owned upon providing the copy to the I/O sub-system and to identify the data as unowned at a second time event.

    摘要翻译: 多处理器系统和方法包括包括多个处理器和处理器存储器系统的处理子系统。 网络可操作以将处理子系统耦合到输入/输出(I / O)子系统。 I / O子系统包括多个I / O接口,每个I / O接口可操作以将外围设备耦合到多处理器系统。 I / O接口各自包括本地存储器,其可操作用于存储来自处理器存储器系统的数据副本,以供对应的外围设备使用,并在第一时间事件中删除副本。 用于处理器的目录可操作以将数据提供给I / O子系统并将数据标识为在第二时间事件中未知的数据。

    Method and apparatus for adapting imaging system operation based on pixel intensity histogram
    33.
    发明授权
    Method and apparatus for adapting imaging system operation based on pixel intensity histogram 有权
    基于像素强度直方图适应成像系统操作的方法和装置

    公开(公告)号:US06542626B1

    公开(公告)日:2003-04-01

    申请号:US09434817

    申请日:1999-11-05

    IPC分类号: G06K900

    摘要: A method and an apparatus for optimizing operating parameters in an ultrasound imaging system in response to the occurrence of predetermined changes in the pixel intensity histogram of successive image frames. In the method, changes in the pixel intensity histogram of successive image frames are monitored and when the detected changes indicate probe movement, re-optimization of the operating parameters is automatically triggered. In the course of re-optimization, mapping, compression, scaling or beamforming parameters can be adjusted based on pixel intensity histogram characteristics determined by the system computer.

    摘要翻译: 一种用于响应于连续图像帧的像素强度直方图中预定变化的发生而优化超声成像系统中的操作参数的方法和装置。 在该方法中,监视连续图像帧的像素强度直方图的变化,并且当检测到的变化指示探测器移动时,自动触发操作参数的重新优化。 在重新优化的过程中,可以基于由系统计算机确定的像素强度直方图特征来调整映射,压缩,缩放或波束成形参数。

    Method and apparatus for analyzing buffer allocation to a device on a peripheral component interconnect bus
    34.
    发明授权
    Method and apparatus for analyzing buffer allocation to a device on a peripheral component interconnect bus 有权
    用于分析对周边组件互连总线上的设备的缓冲器分配的方法和装置

    公开(公告)号:US06397274B1

    公开(公告)日:2002-05-28

    申请号:US09409765

    申请日:1999-09-30

    申请人: Steven C. Miller

    发明人: Steven C. Miller

    IPC分类号: G06F300

    CPC分类号: G06F13/4221 G06F13/161

    摘要: A bridge device (12) in a computer system interconnects with peripheral component interconnect (PCI) devices (14) over a PCI bus (16). The bridge device (12) includes a plurality of read response buffers (10) to provide data to the PCI devices (14). Each of the read response buffers (10) has a plurality of counters/registers (22) associated therewith. The counters/registers (22) measure various parameters associated with the request and retrieval of requested data and speculative data through the read response buffers (10). In response to the parameters measured by the counters/registers (22), the read response buffers (10) can be optimally allocated among the PCI devices (14).

    摘要翻译: 计算机系统中的桥接设备(12)通过PCI总线(16)与外围组件互连(PCI)设备(14)互连。 桥接设备(12)包括多个读取响应缓冲器(10),用于向PCI设备(14)提供数据。 每个读取响应缓冲器(10)具有与其相关联的多个计数器/寄存器(22)。 计数器/寄存器(22)通过读取响应缓冲器(10)来测量与请求相关联的各种参数和检索请求的数据和推测数据。 响应于由计数器/寄存器(22)测量的参数,可以在PCI设备(14)之间最佳地分配读取响应缓冲器(10)。

    System for navigation and editing of electronic records through speech and audio
    35.
    发明授权
    System for navigation and editing of electronic records through speech and audio 失效
    通过语音和音频导航和编辑电子记录的系统

    公开(公告)号:US06347299B1

    公开(公告)日:2002-02-12

    申请号:US09124511

    申请日:1998-07-29

    IPC分类号: G10L2100

    CPC分类号: G06F3/16

    摘要: The present invention provides speech and audio user-computer interface mechanisms for accessing and editing information in electronic records. A mechanism is provided by which the user can direct inputs to any of a variety of fields without following a predetermined order of input. This allows the user to be proactive in making entries rather than simply reacting to requirements set by computer-generated prompts. Audio is provided as feedback to the user, not as a fixed path prompt for the user. This feedback can be in the form of non-verbal auditory signals or synthesized speech. The invention uses audio to inform the user of whether or not the system understood the spoken words or phrases as valid inputs to the electronic record, what the system recognized as the input, and to identify the contents of various fields in the electronic record. The precise wording for the speech inputs can be changed from one implementation of the invention to another, depending on what terminology is most meaningful to users, works best with the speech recognition engine being used, etc. Likewise, the audio outputs from the system, both nonverbal sounds and synthesized speech, used in implementing this invention can vary from one application to another.

    摘要翻译: 本发明提供用于访问和编辑电子记录中的信息的语音和音频用户 - 计算机接口机制。 提供了一种机制,通过该机构,用户可以将输入引导到各种场中的任何一个,而不需要遵循预定的输入顺序。 这允许用户主动地进行输入,而不是简单地响应由计算机生成的提示设置的要求。 音频作为反馈提供给用户,而不是用户的固定路径提示。 这种反馈可以是非言语听觉信号或合成语音的形式。 本发明使用音频通知用户系统是否将口语或短语理解为对电子记录的有效输入,系统识别为输入,以及识别电子记录中的各种领域的内容。 根据对用户最有意义的术语,语音输入的精确字词可以从本发明的一个实施方式改变到另一个实现,最适用于正在使用的语音识别引擎等。同样,来自系统的音频输出, 用于实施本发明的非语音和合成语音都可以从一个应用到另一个应用。

    Method and apparatus for providing dynamically variable time delays for
ultrasound beamformer
    36.
    发明授权
    Method and apparatus for providing dynamically variable time delays for ultrasound beamformer 失效
    为超声波波束形成器提供动态可变时间延迟的方法和装置

    公开(公告)号:US5844139A

    公开(公告)日:1998-12-01

    申请号:US774667

    申请日:1996-12-30

    摘要: A phased array sector scanning ultrasonic system includes a separate receive channel for each respective element in an ultrasonic transducer array. Each receive channel imparts a delay to the echo signal produced by each respective element. The delayed echo signals are summed to form a steered, dynamically focused and dynamically windowed receive beam even when the transmit beam does not emanate from the center of the array. The receiver has a beamformer including a multiplicity of beamformer channels. The beamformer dynamically increases delays to each channel without introducing unwanted discontinuities, by combining and synchronizing a FIFO and an interpolator. The interpolator uses "Wallace tree" adders to accumulate bit-shifted versions of the inputs. The number of additions is less than the number of bits which would be needed to represent equivalent coefficients. This reduces the hardware relative to a conventional implementation which incorporates multipliers with shifts and adds equaling the number of bits in the coefficients.

    摘要翻译: 相控阵扫描超声系统包括用于超声换能器阵列中的每个相应元件的单独的接收通道。 每个接收通道对由每个相应元件产生的回波信号施加延迟。 延迟的回波信号被相加以形成转向,动态聚焦和动态窗口的接收波束,即使当发射波束不从阵列的中心发射时。 接收机具有包括多个波束形成信道的波束形成器。 波束形成器通过组合和同步FIFO和内插器,动态地增加每个通道的延迟,而不会引入不需要的不连续性。 插值器使用“华莱士树”加法器来积累输入的位移版本。 加法的数量小于表示等效系数所需的位数。 这降低了硬件相对于传统实现的结果,该实现结合了具有移位的乘法器并且增加了系数中的比特数。

    Guaranteed bandwidth allocation method in a computer system for
input/output data transfers
    37.
    发明授权
    Guaranteed bandwidth allocation method in a computer system for input/output data transfers 失效
    用于输入/输出数据传输的计算机系统中的保证带宽分配方法

    公开(公告)号:US5784569A

    公开(公告)日:1998-07-21

    申请号:US717581

    申请日:1996-09-23

    摘要: The present invention discloses a novel arbitration procedure for selecting among devices in a computer system requesting access to a single resource such as, for example, a system bus or main memory. The arbitration procedure provides an efficient means for guaranteeing the available system bus bandwidth to devices having high bandwidth requirements. Each device can be allotted a certain amount of bandwidth that is guaranteed to be available for that device within a given time interval. Excess bandwidth not consumed by the guaranteed allotments can be used as remainder (e.g., available but not guaranteed) bandwidth by the devices. The arbitration procedure further provides a guaranteed maximum latency so that no device is prevented from completing data transfers in a timely manner. The arbitration procedure still further provides the ability to dynamically program the amount of the bandwidth that is guaranteed a particular device. The arbitration procedure can be applied to a number of different communication platforms and bus protocols.

    摘要翻译: 本发明公开了一种用于在计算机系统中的设备之间进行选择的新颖的仲裁程序,该计算机系统请求访问诸如系统总线或主存储器的单个资源。 仲裁程序提供了一种有效的手段,用于为具有高带宽要求的设备保证可用的系统总线带宽。 每个设备可以在给定的时间间隔内分配一定数量的带宽,保证该设备可用。 由保证分配不消耗的过量带宽可以被设备用作剩余(例如可用但不能保证)的带宽。 仲裁程序进一步提供有保证的最大等待时间,从而防止任何设备及时完成数据传输。 仲裁程序还提供了动态地编程保证特定设备的带宽量的能力。 仲裁程序可以应用于许多不同的通信平台和总线协议。

    System and method for accelerating anchor point detection
    39.
    发明授权
    System and method for accelerating anchor point detection 有权
    加速锚点检测的系统和方法

    公开(公告)号:US08762345B2

    公开(公告)日:2014-06-24

    申请号:US11756044

    申请日:2007-05-31

    IPC分类号: G06F17/30

    CPC分类号: G06F17/30156 H03M7/3084

    摘要: A sampling based technique for eliminating duplicate data (de-duplication) stored on storage resources, is provided. According to the invention, when a new data set, e.g., a backup data stream, is received by a server, e.g., a storage system or virtual tape library (VTL) system implementing the invention, one or more anchors are identified within the new data set. The anchors are identified using a novel anchor detection circuitry in accordance with an illustrative embodiment of the present invention. Upon receipt of the new data set by, for example, a network adapter of a VTL system, the data set is transferred using direct memory access (DMA) operations to a memory associated with an anchor detection hardware card that is operatively interconnected with the storage system. The anchor detection hardware card may be implemented as, for example, a FPGA is to quickly identify anchors within the data set. As the anchor detection process is performed using a hardware assist, the load on a main processor of the system is reduced, thereby enabling line speed de-duplication.

    摘要翻译: 提供了用于消除存储在存储资源上的重复数据(重复数据删除)的基于抽样的技术。 根据本发明,当服务器(例如,实施本发明的存储系统或虚拟磁带库(VTL))系统接收到诸如备份数据流的新数据集时,在新的数据集内识别出一个或多个锚点 数据集。 根据本发明的说明性实施例,使用新颖的锚定检测电路来识别锚。 在通过例如VTL系统的网络适配器接收到新数据集时,使用直接存储器访问(DMA)操作将数据集传送到与锚定检测硬件卡相关联的存储器,该存储器与存储器可操作地互连 系统。 锚定检测硬件卡可以被实现为例如FPGA快速识别数据集内的锚点。 由于使用硬件辅助进行锚定检测处理,系统的主处理器上的负载减少,从而实现线速度重复数据删除。

    System and method for conveying information
    40.
    发明授权
    System and method for conveying information 有权
    用于传达信息的系统和方法

    公开(公告)号:US08327015B2

    公开(公告)日:2012-12-04

    申请号:US13008635

    申请日:2011-01-18

    IPC分类号: G06F15/16 G06F13/00

    摘要: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, if a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.

    摘要翻译: 用于传送数据的系统和方法包括确定在计算机模块处是否已经接收到交易请求信用的能力,指示可以发送交易请求消息的至少一部分的交易请求信用。 系统和方法还包括确定是否要发送交易请求消息的能力,是否可以发送交易请求消息的至少一部分,并且如果可以发送交易请求消息的至少一部分 被发送。