公开(公告)号：US09218970B2

公开(公告)日：2015-12-22

申请号：US14642968

申请日：2015-03-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rueijer Lin ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  B81C1/00 ,  H01L21/02 ,  H01L21/768

CPC classification number: B81C1/00158 ,  B81B7/008 ,  B81B2207/015 ,  B81B2207/096 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00539 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0742 ,  B81C2203/0778 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

Abstract translation: 在半导体器件制造期间在形成互连的镶嵌工艺中形成氮化钛（TiN）硬掩模的方法，同时控制由TiN硬掩模承载的应力的类型和大小。 TiN硬掩模以多层结构形成，其中通过重复包括TiN和氯PECVD沉积以及N2 / H2等离子体气体处理的工艺循环来连续形成每个子层。 在其形成期间，通过控制TiN子层的数量和等离子体气体处理持续时间来控制由TiN硬掩模承载的应力，使得应力可以平衡在常规制备的TiN硬掩模上预期的预定外部应力 ，这导致沟槽侧壁变形，沟槽开口收缩和间隙填充问题。

公开(公告)号：US20150228605A1

公开(公告)日：2015-08-13

申请号：US14175685

申请日：2014-02-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rueijer Lin ,  Ya-Lien Lee ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/28556 ,  H01L21/76843 ,  H01L21/76847 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Abstract translation: 公开了互连结构和形成互连结构的方法。 互连结构包括在衬底上的导电插塞; 在导电插头上的导电特征，其中导电部件具有第一侧壁，面向第一侧壁的第二侧壁和底表面; 以及具有沿导电特征的第一侧壁的第一部分的第一部分和沿着导电特征的第二侧壁的第二部分，以及沿导电特征的底表面的第三部分。

公开(公告)号：US20140264475A1

公开(公告)日：2014-09-18

申请号：US13925127

申请日：2013-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rueijer Lin ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00158 ,  B81B7/008 ,  B81B2207/015 ,  B81B2207/096 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00539 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0742 ,  B81C2203/0778 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802

Abstract: An integrated circuit device includes a dielectric layer disposed over a semiconductor substrate, the dielectric layer having a sacrificial cavity formed therein, a membrane layer formed onto the dielectric layer, and a capping structure formed on the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.

Abstract translation: 一种集成电路器件，包括设置在半导体衬底上的电介质层，介电层具有形成在其中的牺牲腔，形成在电介质层上的膜层，以及形成在膜层上的封盖结构，从而形成第二腔， 第二腔通过形成于膜层中的通孔连接到牺牲腔。

公开(公告)号：US12094770B2

公开(公告)日：2024-09-17

申请号：US17446398

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yao-Min Liu ,  Ming-Yuan Gao ,  Ming-Chou Chiang ,  Shu-Cheng Chin ,  Huei-Wen Hsieh ,  Kai-Shiang Kuo ,  Yen-Chun Lin ,  Cheng-Hui Weng ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC: H01L21/768 ,  H01L21/304 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76841 ,  H01L21/304 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

公开(公告)号：US11679469B2

公开(公告)日：2023-06-20

申请号：US16550021

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Michael Yen ,  Kao-Feng Liao ,  Hsin-Ying Ho ,  Chun-Wen Hsiao ,  Sheng-Chao Chuang ,  Ting-Hsun Chang ,  Fu-Ming Huang ,  Chun-Chieh Lin ,  Peng-Chung Jangjian ,  Ji James Cui ,  Liang-Guang Chen ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: B24B37/26 ,  B24B37/005 ,  B24B37/24 ,  B24B37/04

CPC classification number: B24B37/26 ,  B24B37/005 ,  B24B37/042 ,  B24B37/24

Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

公开(公告)号：US20210391208A1

公开(公告)日：2021-12-16

申请号：US16902203

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Chi-Hsiang Shen ,  Ting-Hsun Chang ,  Li-Chieh Wu ,  Hung Yen ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Kei-Wei Chen

IPC: H01L21/768 ,  C09G1/02 ,  C09K3/14

Abstract: A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.

公开(公告)号：US10446646B2

公开(公告)日：2019-10-15

申请号：US15613778

申请日：2017-06-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

公开(公告)号：US20170092481A1

公开(公告)日：2017-03-30

申请号：US14870946

申请日：2015-09-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Ming Huang ,  Liang-Guang Chen ,  Ting-Kui Chang ,  Chun-Chieh Lin

IPC: H01L21/02 ,  B08B1/04 ,  H01L21/67 ,  H01L21/306 ,  H01L21/687 ,  B08B1/00 ,  B08B3/04

CPC classification number: H01L21/02043 ,  B08B1/002 ,  B08B1/04 ,  B08B3/04 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/30625 ,  H01L21/67028 ,  H01L21/67046 ,  H01L21/67092 ,  H01L21/687

Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

公开(公告)号：US20160118335A1

公开(公告)日：2016-04-28

申请号：US14523256

申请日：2014-10-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ya-Lien Lee ,  Chun-Chieh Lin

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76813 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via.

Abstract translation: 集成电路结构包括第一导电线，第一导线上的电介质层，电介质层中的扩散阻挡层和介电层中的第二导电线。 第二导线包括扩散阻挡层的第一部分。 通孔位于第二导线之下，并将第二导线电耦合到第一导线。 通孔包括扩散阻挡层的第二部分，扩散阻挡层的第二部分的底端高于通孔的底面。

公开(公告)号：US20150235963A1

公开(公告)日：2015-08-20

申请号：US14706311

申请日：2015-05-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括形成具有多个第一开口的图案化电介质层。 该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。 该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。 该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。 该方法包括去除沟槽掩模层。