公开(公告)号：US20250149485A1

公开(公告)日：2025-05-08

申请号：US19013241

申请日：2025-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/488 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

公开(公告)号：US20250149380A1

公开(公告)日：2025-05-08

申请号：US18415770

申请日：2024-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Eugene Chow Chi Hao ,  Chang-Jung Hsueh ,  Chun-Fu Wu ,  Wen-Hsiung Lu

IPC: H01L21/768 ,  C23C18/38 ,  H01L21/285 ,  H01L21/288

Abstract: A method includes adding a first additive to an electroplating solution, wherein the first additive is a relatively weak suppressing agent; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong suppressing agent; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and depositing copper using the electroplating solution, wherein most of the copper is nanotwinned grains having a (111)-orientation.

公开(公告)号：US12136644B2

公开(公告)日：2024-11-05

申请号：US18063339

申请日：2022-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L23/522 ,  H01L21/311 ,  H01L49/02

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

公开(公告)号：US12134557B2

公开(公告)日：2024-11-05

申请号：US17323147

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhao-Yi Wang ,  Chin-Yu Ku ,  Wen-Hsiung Lu ,  Lung-Kai Mao ,  Ming-Da Cheng

IPC: B81C1/00 ,  B81B3/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

公开(公告)号：US20240321691A1

公开(公告)日：2024-09-26

申请号：US18732879

申请日：2024-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Lun Liu ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chen-En Yen ,  Cheng-Lung Yang ,  Kuanchih Huang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/60

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/60

Abstract: Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the plurality of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

公开(公告)号：US12040256B2

公开(公告)日：2024-07-16

申请号：US18362559

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Lun Liu ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chen-En Yen ,  Cheng-Lung Yang ,  Kuanchih Huang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/60

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/60

Abstract: Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

公开(公告)号：US11935826B2

公开(公告)日：2024-03-19

申请号：US17197483

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Huang ,  Ming-Da Cheng ,  Songbor Lee ,  Jung-You Chen ,  Ching-Hua Kuan ,  Tzy-Kuang Lee

IPC: H01L23/522 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L24/03 ,  H01L28/60 ,  H01L2224/02311 ,  H01L2224/02313

Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

公开(公告)号：US11855017B2

公开(公告)日：2023-12-26

申请号：US17342869

申请日：2021-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/03462 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11849 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2924/3841

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US11742204B2

公开(公告)日：2023-08-29

申请号：US17316008

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20230154880A1

公开(公告)日：2023-05-18

申请号：US18151014

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsu-Lun Liu ,  Kai-Di Wu ,  Su-Fei Lin

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/2101

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.