公开(公告)号：US09105465B2

公开(公告)日：2015-08-11

申请号：US13053803

申请日：2011-03-22

申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L21/02021

摘要： The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

摘要翻译： 本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。 提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。 该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。 该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。 有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

公开(公告)号：US07348210B2

公开(公告)日：2008-03-25

申请号：US10908084

申请日：2005-04-27

申请人： Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Juris Sprogis

发明人： Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Juris Sprogis

IPC分类号： H01L21/00

CPC分类号： H01L23/556 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00014

摘要： A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.

摘要翻译： 一种结构及其形成方法。 该方法包括（a）提供一种结构，其包括（i）电介质层，（ii）与电介质层顶表面直接物理接触的导电接合焊盘，（iii）介电层上的第一钝化层 其中所述第一钝化层包括位于所述导电接合焊盘正上方的第一孔，以及（iv）填充所述第一孔并电耦合到所述导电接合焊盘的导电焊料凸块; 以及（b）在所述第一钝化层上形成第二钝化层，其中第二钝化层与所述导电焊料凸块直接物理接触，并且其中所述导电焊料凸点在所述第二钝化层形成所述第二钝化层之后立即暴露于周围环境 执行钝化层。

公开(公告)号：US20090110881A1

公开(公告)日：2009-04-30

申请号：US11924662

申请日：2007-10-26

申请人： Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC分类号： B32B3/10 ,  B05D5/12

CPC分类号： H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/14136 ,  H01L2224/26152 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/4921 ,  Y10T29/49222 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24347 ,  Y10T428/24479 ,  Y10T428/24529 ,  Y10T428/24545 ,  Y10T428/24612 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/00

摘要： An electrical structure and method of forming. The electrical structure includes a first substrate, first dielectric layer, an underfill layer, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The underfill layer is formed over the top surface of the first dielectric layer and within the first opening. The second substrate is formed over and in contact with the underfill layer.

摘要翻译： 一种电气结构和成型方法。 电结构包括第一衬底，第一介电层，底部填充层和第二衬底。 第一介电层形成在第一基板的顶表面上。 第一电介质层包括延伸穿过所述第一电介质层的顶表面和底表面的第一开口。 底部填充层形成在第一介电层的顶表面上并且在第一开口内。 第二衬底形成在底部填充层上并与底部填充层接触。

公开(公告)号：US20130008699A1

公开(公告)日：2013-01-10

申请号：US13615826

申请日：2012-09-14

申请人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H05K1/11 ,  H05K1/09 ,  H05K1/03

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012

摘要： A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.

摘要翻译： 一个结构。 该结构包括：第一电介质层，其包括顶部电介质表面; 在所述第一电介质层上的导电线; 在所述第一电介质层和所述导电线上的第二电介质层; 所述第二电介质层和所述导电线上的限界冶金（BLM）区域使得所述BLM区电连接到所述导电线; 和BLM区域上的焊球。 BLM区域的特征在于，平行于顶部电介质表面并且完全在BLM区域中的最长直线段的长度不超过预定的最大值，其中预定的最大值最多为 BLM区域的最大水平尺寸的一半在平行于顶部电介质表面的水平方向上测量。

公开(公告)号：US08299611B2

公开(公告)日：2012-10-30

申请号：US12547540

申请日：2009-08-26

申请人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012

摘要： A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.

摘要翻译： 焊球结构及其形成方法。 该结构包括（i）第一介电层，其包括顶部电介质表面，（ii）导电线，（iii）第二介电层，（iv）球限制冶金（BLM）区域和（v ）焊球。 BLM区域电连接到导电线和焊球。 BLM区域具有与第一介电层的顶部电介质表面平行且完全在BLM区域中的最长直线段的长度不超过预定的最大值的特性。 预定的最大值为平行于第一介电层的顶部电介质表面的水平方向上测量的BLM区域的最大水平尺寸的至多一半。

公开(公告)号：US07545050B1

公开(公告)日：2009-06-09

申请号：US12183369

申请日：2008-07-31

申请人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

发明人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05655 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.

摘要翻译： 提供用于半导体芯片的封装的设计结构，其使从芯片到衬底或芯片到卡互连的差分热膨胀产生的应力和应变最小化。 在最终铜金属化水平之上的一组改进的设计结构通孔，可减轻半导体组装和测试期间的冲击。 其他实施例包括具有变化的微机械支撑结构的设计结构，其进一步最小化半导体封装中的应力和应变。

公开(公告)号：US08592976B2

公开(公告)日：2013-11-26

申请号：US13615826

申请日：2012-09-14

申请人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012

摘要： A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.

摘要翻译： 一个结构。 该结构包括：第一电介质层，其包括顶部电介质表面; 在所述第一电介质层上的导电线; 在所述第一电介质层和所述导电线上的第二电介质层; 所述第二电介质层和所述导电线上的限界冶金（BLM）区域使得所述BLM区电连接到所述导电线; 和BLM区域上的焊球。 BLM区域的特征在于，平行于顶部电介质表面并且完全在BLM区域中的最长直线段的长度不超过预定的最大值，其中预定的最大值最多为 BLM区域的最大水平尺寸的一半在平行于顶部电介质表面的水平方向上测量。

公开(公告)号：US20100258940A1

公开(公告)日：2010-10-14

申请号：US12547540

申请日：2009-08-26

申请人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Charles L. Arvin ,  Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012

摘要： A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.

摘要翻译： 焊球结构及其形成方法。 该结构包括（i）包括顶部电介质表面的第一电介质层，（ii）导电线，（iii）第二电介质层，（iv）球限制冶金（BLM）区域和（v ）焊球。 BLM区域电连接到导电线和焊球。 BLM区域具有与第一介电层的顶部电介质表面平行且完全在BLM区域中的最长直线段的长度不超过预定的最大值的特性。 预定的最大值为平行于第一介电层的顶部电介质表面的水平方向上测量的BLM区域的最大水平尺寸的至多一半。

公开(公告)号：US07439170B1

公开(公告)日：2008-10-21

申请号：US12044692

申请日：2008-03-07

申请人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

发明人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05655 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.

摘要翻译： 提供用于半导体芯片的封装的设计结构，其使从芯片到衬底或芯片到卡互连的差分热膨胀产生的应力和应变最小化。 在最终铜金属化水平之上的一组改进的设计结构通孔，可减轻半导体组装和测试期间的冲击。 其他实施例包括具有变化的微机械支撑结构的设计结构，其进一步最小化半导体封装中的应力和应变。

公开(公告)号：US08927869B2

公开(公告)日：2015-01-06

申请号：US13444343

申请日：2012-04-11

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H05K1/00

CPC分类号： H01L24/05 ,  H01B3/306 ,  H01B3/307 ,  H01L21/02118 ,  H01L21/76877 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/48

摘要： Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

摘要翻译： 公开了使用有机绝缘材料的引线键合半导体结构和制造方法。 该方法包括在有机绝缘体层中形成金属布线层。 该方法还包括在有机绝缘体层上形成保护层。 该方法还包括在金属布线层上的有机绝缘体层中形成通孔。 该方法还包括在通孔中和保护层上沉积金属层。 该方法还包括用对有机绝缘体层有害的蚀刻化学物图案化金属层。