公开(公告)号：US07439170B1

公开(公告)日：2008-10-21

申请号：US12044692

申请日：2008-03-07

申请人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

发明人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05655 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.

摘要翻译： 提供用于半导体芯片的封装的设计结构，其使从芯片到衬底或芯片到卡互连的差分热膨胀产生的应力和应变最小化。 在最终铜金属化水平之上的一组改进的设计结构通孔，可减轻半导体组装和测试期间的冲击。 其他实施例包括具有变化的微机械支撑结构的设计结构，其进一步最小化半导体封装中的应力和应变。

公开(公告)号：US07545050B1

公开(公告)日：2009-06-09

申请号：US12183369

申请日：2008-07-31

申请人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

发明人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05655 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.

摘要翻译： 提供用于半导体芯片的封装的设计结构，其使从芯片到衬底或芯片到卡互连的差分热膨胀产生的应力和应变最小化。 在最终铜金属化水平之上的一组改进的设计结构通孔，可减轻半导体组装和测试期间的冲击。 其他实施例包括具有变化的微机械支撑结构的设计结构，其进一步最小化半导体封装中的应力和应变。

公开(公告)号：US20090256257A1

公开(公告)日：2009-10-15

申请号：US12102035

申请日：2008-04-14

申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  David L. Questad ,  Wolfgang Sauter

发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  David L. Questad ,  Wolfgang Sauter

IPC分类号： H01L23/52 ,  H01L23/488 ,  H01L21/44

CPC分类号： H01L23/53295 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A structure and a method for forming the same. The structure includes a first dielectric layer, an electrically conductive bond pad on the first dielectric layer, and a second dielectric layer on top of the first dielectric layer and the electrically conductive bond pad. The electrically conductive bond pad is sandwiched between the first and second dielectric layers. The second dielectric layer includes N separate final via openings such that a top surface of the electrically conductive bond pad is exposed to a surrounding ambient through each final via opening of the N separate final via openings. N is a positive integer greater than 1.

摘要翻译： 一种结构及其形成方法。 该结构包括第一电介质层，第一电介质层上的导电接合焊盘，以及在第一电介质层和导电接合焊盘顶部的第二电介质层。 导电接合焊盘夹在第一和第二电介质层之间。 第二电介质层包括N个独立的最终通路孔，使得导电接合焊盘的顶表面暴露于通过N个单独的最终通孔的每个最终通孔的周围环境。 N是大于1的正整数。

公开(公告)号：US07256503B2

公开(公告)日：2007-08-14

申请号：US11276380

申请日：2006-02-27

申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  David L. Questad

发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  David L. Questad

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81194 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83194 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/3512

摘要： A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.

摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括（a）基板和（b）包括N个芯片焊球，N是正整数的芯片，并且N个芯片焊球与基板电接触。 半导体结构还包括（c）分别在芯片的第一，第二，第三和第四角部处并夹在芯片和基板之间的第一，第二，第三和第四角底部填充区域。 半导体结构还包括（d）夹在芯片和衬底之间的主要底部填充区域。 第一，第二，第三和第四角底部填充区域，并且主底部填充区域基本上占据芯片和基板之间的整个空间。 第一，第二，第三和第四角底部填充区域的角底层填充材料与主要底部填充区域的主要底部填充材料不同。

公开(公告)号：US20120241916A1

公开(公告)日：2012-09-27

申请号：US13053803

申请日：2011-03-22

申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L29/02 ,  H01L21/302

CPC分类号： H01L21/02021

摘要： The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

摘要翻译： 本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。 提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。 该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。 该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。 有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

公开(公告)号：US08575007B2

公开(公告)日：2013-11-05

申请号：US13073181

申请日：2011-03-28

申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Thomas Anthony Wassick

发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Thomas Anthony Wassick

IPC分类号： H01L21/326 ,  H01L21/44

CPC分类号： H01L24/14 ,  G06F17/5068 ,  G06F2217/40 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05563 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/13006 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00012 ,  H01L2224/05552

摘要： The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.

摘要翻译： 本发明包括用于设计倒装芯片的方法及其结果的实施例。 起点是具有半导体衬底的倒装芯片，一个或多个布线层，以及用于接收和发送电流的多个I / O接触焊盘（最后的金属焊盘/接合焊盘）。 还存在用于将I / O接触焊盘连接到另一衬底的多个C4凸块。 然后，确定多个C4凸块中的哪个C4具有达到或超过阈值磁敏度水平的电迁移损伤的敏感性水平，并且作为响应，电镀具有高电流承载能力的导电结构（例如 铜柱，铜基座或部分铜基座）连接到相应的I / O接触焊盘上，并将焊球添加到导电结构的顶部。 所得到的结构是倒装芯片，其中只有少量的C4凸块使用增强的C4（例如铜基座）来减少缺陷的机会。

公开(公告)号：US20120248604A1

公开(公告)日：2012-10-04

申请号：US13073181

申请日：2011-03-28

申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Thomas Anthony Wassick

发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Thomas Anthony Wassick

IPC分类号： H01L23/488 ,  G06F17/50

CPC分类号： H01L24/14 ,  G06F17/5068 ,  G06F2217/40 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05563 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/13006 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00012 ,  H01L2224/05552

摘要： The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.

摘要翻译： 本发明包括用于设计倒装芯片的方法及其结果的实施例。 起点是具有用于接收和发送电流的半导体衬底，一个或多个布线层和多​​个I / O接触焊盘（最后的金属焊盘/接合焊盘）的倒装芯片。 还存在用于将I / O接触焊盘连接到另一衬底的多个C4凸块。 然后，确定多个C4凸块中的哪个C4具有达到或超过阈值磁敏度水平的电迁移损伤的敏感性水平，并且作为响应，电镀具有高电流承载能力的导电结构（例如 铜柱，铜基座或部分铜基座）连接到相应的I / O接触焊盘上，并将焊球添加到导电结构的顶部。 所得到的结构是倒装芯片，其中只有少量的C4凸块使用增强的C4（例如铜基座）来减少缺陷的机会。

公开(公告)号：US09105465B2

公开(公告)日：2015-08-11

申请号：US13053803

申请日：2011-03-22

申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L21/02021

摘要： The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

摘要翻译： 本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。 提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。 该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。 该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。 有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

公开(公告)号：US07859122B2

公开(公告)日：2010-12-28

申请号：US12102035

申请日：2008-04-14

申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  David L. Questad ,  Wolfgang Sauter

发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  David L. Questad ,  Wolfgang Sauter

IPC分类号： H01L23/48

CPC分类号： H01L23/53295 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A structure and a method for forming the same. The structure includes a first dielectric layer, an electrically conductive bond pad on the first dielectric layer, and a second dielectric layer on top of the first dielectric layer and the electrically conductive bond pad. The electrically conductive bond pad is sandwiched between the first and second dielectric layers. The second dielectric layer includes N separate final via openings such that a top surface of the electrically conductive bond pad is exposed to a surrounding ambient through each final via opening of the N separate final via openings. N is a positive integer greater than 1.

摘要翻译： 一种结构及其形成方法。 该结构包括第一电介质层，第一电介质层上的导电接合焊盘，以及在第一电介质层和导电接合焊盘顶部的第二电介质层。 导电接合焊盘夹在第一和第二电介质层之间。 第二电介质层包括N个独立的最终通路孔，使得导电接合焊盘的顶表面暴露于通过N个单独的最终通孔的每个最终通孔的周围环境。 N是大于1的正整数。

公开(公告)号：US08637392B2

公开(公告)日：2014-01-28

申请号：US12700863

申请日：2010-02-05

申请人： Charles L. Arvin ,  Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Brian R. Sundlof

发明人： Charles L. Arvin ,  Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Brian R. Sundlof

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/119 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01026 ,  H01L2924/01032 ,  H01L2924/00012 ,  H01L2924/00

摘要： A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

摘要翻译： 焊接互连结构设置有不可润湿的侧壁及其制造方法。 该方法包括在下面的表面上形成镍或镍合金支柱。 该方法还包括修改镍或镍合金柱的侧壁以防止在侧壁上的焊料润湿。