公开(公告)号：US20050272254A1

公开(公告)日：2005-12-08

申请号：US11184404

申请日：2005-07-18

Applicant: Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen Chen ,  Barry Chin ,  Gene Kohara

Inventor： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen Chen ,  Barry Chin ,  Gene Kohara

IPC: C23C14/06 ,  C23C14/16 ,  C23C14/32 ,  H01L21/285 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/02183 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/02266 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876

Abstract: We have discovered a method of providing a thin approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 μΩ cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.

Abstract translation: 我们已经发现了一种提供大约约2埃至大约100埃的Ta N种子层的薄膜的方法，当钽沉积在Ta上时可用于诱导形成α钽， SUB> N 种子层。 此外，Ta N N种子层在30μΩ·cm的范围内显示低电阻率，并且可以在不存在α钽层的情况下用作低电阻率阻挡层。 在该方法的一个实施方案中，TaN膜在其表面上形成Ta N N种子层。 在该方法的另一个实施方案中，在其表面上改变Ta膜以形成Ta N N种子层。

公开(公告)号：US20050031784A1

公开(公告)日：2005-02-10

申请号：US10931865

申请日：2004-09-01

Applicant: Peijun Ding ,  Tony Chiang ,  Tse-Yong Yao ,  Barry Chin

Inventor： Peijun Ding ,  Tony Chiang ,  Tse-Yong Yao ,  Barry Chin

IPC: C25D5/34 ,  C25D3/00 ,  C25D7/12 ,  H01L21/28 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  C23C14/00 ,  H05H1/24

CPC classification number: H01L21/76846 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877

Abstract: The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.

Abstract translation: 本发明通常提供了一种用于制备用于电化学沉积的表面的方法，其包括在表面上形成高导电阻挡层并在高导电阻挡层上沉积种子层。 本发明的另一方面提供了一种用于在基板上填充结构的方法，包括在所述结构的一个或多个表面上沉积高电导阻挡层，在所述阻挡层上沉积晶种层，以及电化学沉积金属以填充所述结构 。

公开(公告)号：US06559061B2

公开(公告)日：2003-05-06

申请号：US09928891

申请日：2001-08-13

Applicant: Imran Hashim ,  Tony Chiang ,  Barry Chin

Inventor： Imran Hashim ,  Tony Chiang ,  Barry Chin

IPC: H01L21302

CPC classification number: H01L21/76844 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

公开(公告)号：US6160315A

公开(公告)日：2000-12-12

申请号：US478721

申请日：2000-01-06

Applicant: Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

Inventor： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

IPC: C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76834 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/2855 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A copper via structure formed when copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide but also extends into the oxide a distance of about 100 nm. The alloying metal oxide having a thickness of about 6 nm on the oxide sidewalls encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.

Abstract translation: 当铜和少量的合金金属如镁或铝形成的铜通孔结构在其表面的至少一部分上被分散在具有氧化物的基底上。 在沉积期间晶片保持在升高的温度下，或者溅射膜被退火而晶片不暴露于环境中。 由于高温，合金金属扩散到表面。 如果表面暴露于低的氧分压或接触二氧化硅，则镁或铝形成薄的稳定氧化物，但也延伸到氧化物中约100nm的距离。 在氧化物侧壁上具有约6nm厚度的合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障，以形成二氧化硅以上的粘合层，并且用作后续生长铜的种子层， 例如，通过电镀。

公开(公告)号：US09129894B2

公开(公告)日：2015-09-08

申请号：US13621371

申请日：2012-09-17

Applicant: Imran Hashim ,  Tony Chiang ,  Vidyut Gopal ,  Yun Wang

Inventor： Imran Hashim ,  Tony Chiang ,  Vidyut Gopal ,  Yun Wang

IPC: G11C11/21 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Abstract translation: 提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。 转向元件可以是与开关层串联连接的晶体管。 由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。 包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。 在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。 存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。 一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

公开(公告)号：US08900422B2

公开(公告)日：2014-12-02

申请号：US12921776

申请日：2009-04-17

Applicant: Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

Inventor： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: B05D5/12 ,  C23C14/34 ,  H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/314 ,  H01L21/316 ,  H01L27/108 ,  H01L21/02

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US08878151B2

公开(公告)日：2014-11-04

申请号：US13331650

申请日：2011-12-20

Applicant: Tony Chiang

Inventor： Tony Chiang

IPC: H01L45/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: H01L45/146 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79

Abstract: Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.

Abstract translation: 提供多个非易失性存储器元件。 多个非易失性存储器元件包含多个层。 每个层可以基于不同的双稳态材料。 双稳态材料可以是电阻式开关材料，例如电阻式开关金属氧化物。 可选导体层和电流导向元件可以与双稳电阻开关金属氧化物层串联连接。

公开(公告)号：US08877550B2

公开(公告)日：2014-11-04

申请号：US13371220

申请日：2012-02-10

Applicant: Pragati Kumar ,  Sean Barstow ,  Sunil Shanker ,  Tony Chiang

Inventor： Pragati Kumar ,  Sean Barstow ,  Sunil Shanker ,  Tony Chiang

IPC: H01L45/00 ,  H01L27/04 ,  H01L27/24

CPC classification number: H01L45/1633 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.

Abstract translation: 提供电阻式开关非易失性存储元件。 可以使用快速热退火技术来加热含金属层和用于存储元件的氧化物层。 在加热期间，氧化物层可能分解并与含金属层反应。 来自分解氧化物层的氧可以从含金属的层与金属形成金属氧化物。 所得到的金属氧化物可以表现出用于电阻式开关存储元件的电阻式开关。

公开(公告)号：US08787066B2

公开(公告)日：2014-07-22

申请号：US13281777

申请日：2011-10-26

Applicant: Yun Wang ,  Tony Chiang ,  Imran Hashim ,  Vidyut Gopal

Inventor： Yun Wang ,  Tony Chiang ,  Imran Hashim ,  Vidyut Gopal

IPC: G11C11/00

CPC classification number: H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: Methods for producing RRAM resistive switching elements having optimal switching behavior include crystalline phase structural changes. Structural changes indicative of optimal switching behavior include hafnium oxide phases in an interfacial region between a resistive switching layer and an electrode.

Abstract translation: 具有最佳切换行为的RRAM电阻式开关元件的制造方法包括晶相结构变化。 指示最佳切换行为的结构变化包括在电阻式开关层和电极之间的界面区域中的氧化铪相。

公开(公告)号：US08728879B2

公开(公告)日：2014-05-20

申请号：US13547856

申请日：2012-07-12

Applicant: Bob Kong ,  Tony Chiang ,  Chi-I Lang ,  Zhi-Wen Wen Sun ,  Jinhong Tong

Inventor： Bob Kong ,  Tony Chiang ,  Chi-I Lang ,  Zhi-Wen Wen Sun ,  Jinhong Tong

IPC: H01L21/20

CPC classification number: H01L21/02068 ,  C23C18/1651 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76852 ,  H01L21/76874

Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.