公开(公告)号：US20050275750A1

公开(公告)日：2005-12-15

申请号：US10863994

申请日：2004-06-09

申请人： Salman Akram ,  Peter Benson ,  Warren Farnworth ,  William Hiatt

发明人： Salman Akram ,  Peter Benson ,  Warren Farnworth ,  William Hiatt

IPC分类号： H01L27/146 ,  H01L31/0232 ,  H04N5/225 ,  H04N9/64

CPC分类号： H04N5/2253 ,  H01L27/14609 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/02325 ,  H01L2224/48091 ,  H04N5/2254 ,  H01L2924/00014

摘要： The following disclosure describes several embodiments of (1) methods for wafer-level packaging of microelectronic imagers, (2) methods of forming electrically conductive interconnects in microelectronic imagers, (3) methods for forming optical devices for microelectronic imagers, and (4) microelectronic imagers that have been packaged using wafer-level packaging processes. Wafer-level packaging of microelectronic imagers is expected to significantly enhance the efficiency of manufacturing microelectronic imagers because a plurality of imagers can be packaged simultaneously using highly accurate and efficient processes developed for packaging semiconductor devices. Moreover, wafer-level packaging of microelectronic imagers is expected to enhance the quality and performance of such imagers because the semiconductor fabrication processes can reliably align an optical device with an image sensor and space the optical device apart from the image sensor by a desired distance with a higher degree of precision.

摘要翻译： 以下公开内容描述了（1）用于微电子成像器的晶片级封装的方法的几个实施例，（2）在微电子成像器中形成导电互连的方法，（3）用于形成微电子成像器的光学器件的方法，以及（4）微电子 使用晶圆级封装工艺封装的成像仪。 预期微电子成像器的晶片级封装将显着提高制造微电子成像器的效率，因为可以使用开发用于封装半导体器件的高精度和有效的工艺同时封装多个成像器。 此外，微电子成像器的晶片级封装有望提高这种成像器的质量和性能，因为半导体制造工艺可以可靠地将光学器件与图像传感器对准，并将光学器件与图像传感器分开，并将其与图像传感器隔开期望的距离， 更高的精度。

公开(公告)号：US20080020505A1

公开(公告)日：2008-01-24

申请号：US11863087

申请日：2007-09-27

申请人： Salman Akram ,  Charles Watkins ,  Kyle Kirby ,  Alan Wood ,  Wiliam Hiatt

发明人： Salman Akram ,  Charles Watkins ,  Kyle Kirby ,  Alan Wood ,  Wiliam Hiatt

IPC分类号： H01L21/00

CPC分类号： H01L27/146 ,  H01L21/76898 ,  H01L27/14618 ,  H01L27/148 ,  H01L31/02016 ,  H01L2224/48227 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/00

摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.

摘要翻译： 本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。 在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。 接合焊盘由衬底承载并电耦合到集成电路。 导电晶片互连延伸穿过衬底并与接合焊盘接触。 互连可以包括完全延伸穿过衬底和接合焊盘的通道，沉积到通道中并与衬底接触的电介质衬垫，沉积在电介质衬垫的至少一部分上的第一和第二导电层以及导电 在第二导电层的至少一部分上沉积到通道中并且电耦合到接合焊盘的填充材料。

公开(公告)号：US20060043509A1

公开(公告)日：2006-03-02

申请号：US10925502

申请日：2004-08-24

申请人： Charles Watkins ,  David Hembree ,  Peter Benson ,  Salman Akram

发明人： Charles Watkins ,  David Hembree ,  Peter Benson ,  Salman Akram

IPC分类号： H01L21/00 ,  H01L27/14 ,  H01L31/0232

CPC分类号： H01L27/14625 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/1469 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging device further includes a cover over the image sensor and a plurality of interconnects in and/or on the cover that are electrically coupled to corresponding bond-pads of the die. The interconnects provide external electrical contacts for the bond-pads of the die. The interconnects can extend through the cover or along a surface of the cover.

公开(公告)号：US20060255418A1

公开(公告)日：2006-11-16

申请号：US11409058

申请日：2006-04-24

申请人： Charles Watkins ,  David Hembree ,  Peter Benson ,  Salman Akram

发明人： Charles Watkins ,  David Hembree ,  Peter Benson ,  Salman Akram

IPC分类号： H01L31/0232 ,  H01L31/0203

CPC分类号： H01L27/14625 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/1469 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging device further includes a cover over the image sensor and a plurality of interconnects in and/or on the cover that are electrically coupled to corresponding bond-pads of the die. The interconnects provide external electrical contacts for the bond-pads of the die. The interconnects can extend through the cover or along a surface of the cover.

摘要翻译： 本文公开了微电子成像装置和包装微电子成像装置的方法。 在一个实施例中，微电子成像装置包括具有集成电路的微电子管芯，电耦合到集成电路的图像传感器，以及电耦合到集成电路的多个接合焊盘。 所述成像装置还包括覆盖在所述图像传感器上的盖和在所述盖中和/或盖上的多个互连件，其电耦合到所述管芯的相应接合焊盘。 互连件为模具的焊盘提供外部电触头。 互连可以延伸穿过盖或沿着盖的表面。

公开(公告)号：US20080011815A1

公开(公告)日：2008-01-17

申请号：US11777137

申请日：2007-07-12

申请人： Kyle Kirby ,  Salman Akram ,  Daniel Cram ,  Roy Lange ,  Warren Farnworth

发明人： Kyle Kirby ,  Salman Akram ,  Daniel Cram ,  Roy Lange ,  Warren Farnworth

IPC分类号： B23K31/02

CPC分类号： B23K1/085 ,  B23K1/0016 ,  B23K3/0653 ,  B23K2101/40

摘要： Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder bath, a nozzle for producing a solder wave, and a jig for orienting a substrate in a substantially vertical orientation and placing the substrate in contact with a cascading solder wave. In another wave soldering apparatus, a jig orients a semiconductor wafer in a substantially horizontal orientation in contact with the solder wave. Another soldering apparatus includes a tank comprising molten solder and a fixture configured to orient one or more semiconductor wafers in a substantially vertical orientation. Methods of placing semiconductor wafers or other substrates in contact with solder using the devices of the present invention are also disclosed.

摘要翻译： 描述了将半导体晶片或其它基板与焊料接触的方法和装置。 波峰焊装置包括焊料槽，用于产生焊波的喷嘴和用于使基板垂直定向的夹具，并使基板与级联焊波接触。 在另一种波峰焊装置中，夹具使得与焊波接触的大致水平取向的半导体晶片。 另一个焊接装置包括一个包含熔融焊料和一个被配置为使一个或多个半导体晶片呈基本垂直取向取向的夹具的罐。 还公开了使用本发明的装置将半导体晶片或其它基板与焊料接触的方法。

公开(公告)号：US20060043154A1

公开(公告)日：2006-03-02

申请号：US11140420

申请日：2005-05-27

申请人： Kyle Kirby ,  Salman Akram ,  Daniel Cram ,  Roy Lange ,  Warren Farnworth

发明人： Kyle Kirby ,  Salman Akram ,  Daniel Cram ,  Roy Lange ,  Warren Farnworth

IPC分类号： B23K31/02 ,  B23K1/08

CPC分类号： B23K1/085 ,  B23K1/0016 ,  B23K3/0653 ,  B23K2101/40

摘要： Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder bath, a nozzle for producing a solder wave, and a jig for orienting a substrate in a substantially vertical orientation and placing the substrate in contact with a cascading solder wave. In another wave soldering apparatus, a jig orients a semiconductor wafer in a substantially horizontal orientation in contact with the solder wave. Another soldering apparatus includes a tank comprising molten solder and a fixture configured to orient one or more semiconductor wafers in a substantially vertical orientation. Methods of placing semiconductor wafers or other substrates in contact with solder using the devices of the present invention are also disclosed.

摘要翻译： 描述了将半导体晶片或其它基板与焊料接触的方法和装置。 波峰焊装置包括焊料槽，用于产生焊波的喷嘴和用于使基板垂直定向的夹具，并使基板与级联焊波接触。 在另一种波峰焊装置中，夹具使得与焊波接触的大致水平取向的半导体晶片。 另一个焊接装置包括一个包含熔融焊料和一个被配置为使一个或多个半导体晶片呈基本垂直取向取向的夹具的罐。 还公开了使用本发明的装置将半导体晶片或其它基板与焊料接触的方法。

公开(公告)号：US20050275049A1

公开(公告)日：2005-12-15

申请号：US10864974

申请日：2004-06-10

申请人： Kyle Kirby ,  Salman Akram ,  William Hiatt

发明人： Kyle Kirby ,  Salman Akram ,  William Hiatt

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L27/146 ,  H01L31/0203 ,  H01L31/0232

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L27/14618 ,  H01L27/14625 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H04N5/2257 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending partially through the substrate to the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, a conductive layer deposited onto at least a portion of the dielectric liner, a wetting agent deposited onto at least a portion of the conductive layer, and a conductive fill material deposited into the passage and electrically coupled to the bond-pad.

摘要翻译： 本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。 在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。 接合焊盘由衬底承载并电耦合到集成电路。 导电晶片互连部分地穿过衬底延伸并与焊盘接触。 互连可以包括部分地延伸穿过衬底到接合焊盘的通道，沉积到通道中并与衬底接触的介电衬垫，沉积在电介质衬垫的至少一部分上的导电层，沉积在电介质衬垫上的润湿剂 所述导电层的至少一部分以及沉积到所述通道中并电耦合到所述接合焊盘的导电填充材料。

公开(公告)号：US5559444A

公开(公告)日：1996-09-24

申请号：US452990

申请日：1995-05-30

申请人： Warren Farnworth ,  Salman Akram ,  David Hembree

发明人： Warren Farnworth ,  Salman Akram ,  David Hembree

IPC分类号： G01R1/04 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  G01R1/02

CPC分类号： G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/80 ,  H05K3/4007 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423 ,  Y10T29/49155

摘要： A method and apparatus for testing unpackaged semiconductor dice is provided. The method includes forming an interconnect-alignment fixture for use in a test apparatus adapted to hold and apply test signals to the die during burn-in and full functionality testing. The interconnect-alignment fixture includes an interconnect plate formed out of a material such as silicon. The interconnect plate includes raised contact members covered with a conductive layer and adapted to penetrate contact locations on the die to a limited penetration depth. The interconnect-alignment fixture also includes an alignment plate formed with etched alignment openings for aligning contact locations on the die with the contact members on the interconnect plate during the test procedure. In addition, the alignment plate includes access openings for establishing an electrical connection to the contact members on the interconnect plate using wire bonding or mechanical electrical connectors. The interconnect plate and alignment plate are fabricated at the wafer level and then singulated using semiconductor circuit fabrication techniques.

摘要翻译： 提供了一种用于测试未封装的半导体晶片的方法和装置。 该方法包括形成用于测试装置中的互连对准夹具，其适于在老化和全功能测试期间保持并施加测试信号至模具。 互连对准夹具包括由诸如硅的材料形成的互连板。 互连板包括覆盖有导电层的凸起的接触构件，并且适于将模具上的接触位置穿透到有限的穿透深度。 互连对准夹具还包括形成有蚀刻对准开口的对准板，用于在测试过程期间将模具上的接触位置与互连板上的接触构件对准。 此外，对准板包括进入开口，用于使用引线接合或机械电连接器建立与互连板上的接触构件的电连接。 互连板和对准板在晶片级制造，然后使用半导体电路制造技术进行分割。

公开(公告)号：US20070037418A1

公开(公告)日：2007-02-15

申请号：US11585462

申请日：2006-10-24

申请人： Salman Akram ,  David Hembree ,  Warren Farnworth

发明人： Salman Akram ,  David Hembree ,  Warren Farnworth

IPC分类号： H01R12/00

CPC分类号： H01R13/2421 ,  G01R1/0466 ,  G01R1/0483 ,  H01L2924/0002 ,  H01R12/714 ,  H01R2201/20 ,  H05K7/1061 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/4914 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  Y10T29/49224 ,  Y10T29/53174 ,  H01L2924/00

摘要： A socket contact formation process comprises forming a contact head from a conductive material, forming a contact body from a semiconductive material configured to be electrically conductive; and joining the contact head and the contact body.

公开(公告)号：US20070132105A1

公开(公告)日：2007-06-14

申请号：US11702286

申请日：2007-02-05

申请人： Salman Akram ,  James Wark ,  William Hiatt

发明人： Salman Akram ,  James Wark ,  William Hiatt

IPC分类号： H01L23/48

CPC分类号： H01L21/76879 ,  C23C18/1607 ,  C23C18/1637 ,  C23C18/1831 ,  C23C18/1834 ,  C23C18/34 ,  C23C18/36 ,  H01L21/288 ,  H01L21/76898 ,  H01L2924/00013 ,  Y10T428/12528 ,  Y10T428/24917 ,  H01L2224/29099

摘要： A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.