公开(公告)号：US07294920B2

公开(公告)日：2007-11-13

申请号：US11186840

申请日：2005-07-22

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

IPC分类号： H01L23/04

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/82

摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

摘要翻译： 本发明涉及一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。

公开(公告)号：US20070152318A1

公开(公告)日：2007-07-05

申请号：US11308658

申请日：2006-04-19

申请人： Chia-Wen Chiang ,  Shou-Lung Chen

发明人： Chia-Wen Chiang ,  Shou-Lung Chen

IPC分类号： H01L23/24

CPC分类号： H01L23/3135 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention provides a chip package structure, which includes a chip and a buffering compound, wherein the chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces joining the active surface and the back surface. The buffering compound is disposed at least on the active surface and the back surface, and the buffering compound possesses Young's modulus between 1 MPa and 1 GPa. The buffering compound contributes to reduce the negative effect of thermal stresses and accordingly advance reliability of the chip package structure. In addition, the present invention further provides a chip package process and based on the same reason the process is able to achieve a better production yield by forming a buffering compound surrounding the chip.

摘要翻译： 本发明提供了一种芯片封装结构，其包括芯片和缓冲化合物，其中芯片具有活性表面，与活性表面相对的背面和连接有效表面和背表面的多个侧表面。 缓冲化合物至少设置在活性表面和背面上，缓冲化合物的杨氏模量在1MPa和1GPa之间。 缓冲化合物有助于减少热应力的负面影响，从而提高芯片封装结构的可靠性。 此外，本发明还提供一种芯片封装工艺，并且基于相同的原因，该工艺能够通过形成围绕芯片的缓冲化合物来实现更好的生产产量。

公开(公告)号：US20070108572A1

公开(公告)日：2007-05-17

申请号：US11410986

申请日：2006-04-26

申请人： Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuah Cheng

发明人： Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuah Cheng

IPC分类号： H01L21/00

CPC分类号： H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2201/09909 ,  H01L2924/00

摘要： A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

摘要翻译： 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。

公开(公告)号：US20060157864A1

公开(公告)日：2006-07-20

申请号：US11269613

申请日：2005-11-09

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L24/97 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/82

摘要： The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

公开(公告)号：US20060110853A1

公开(公告)日：2006-05-25

申请号：US11252572

申请日：2005-10-19

申请人： Shou-Lung Chen ,  Cheng-Ta Ko

发明人： Shou-Lung Chen ,  Cheng-Ta Ko

IPC分类号： H01L21/50 ,  H01L21/30

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/8203 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/82 ,  H01L2924/00

摘要： A structure of embedded active components and the manufacturing method thereof are provided. The manufacturing steps involve providing a molding plate, and setting several active components on the molding plate as first. A dielectric layer covers the molding plate to cap the active components. An electric circuit is formed on the dielectric layer, in contact with the active components. Finally, the structure with embedded active components is released from the molding plate.

公开(公告)号：US08048716B2

公开(公告)日：2011-11-01

申请号：US12382526

申请日：2009-03-18

申请人： Shou-Lung Chen ,  Cheng-Ta Ko

发明人： Shou-Lung Chen ,  Cheng-Ta Ko

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/8203 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/82 ,  H01L2924/00

摘要： A structure of embedded active components and the manufacturing method thereof are provided. The manufacturing steps involve providing a molding plate, and setting several active components on the molding plate as first. A dielectric layer covers the molding plate to cap the active components. An electric circuit is formed on the dielectric layer, in contact with the active components. Finally, the structure with embedded active components is released from the molding plate.

摘要翻译： 提供嵌入式有源元件的结构及其制造方法。 制造步骤包括提供模制板，并且首先在模制板上设置若干活性组分。 电介质层覆盖模制板以盖住活性组分。 在电介质层上形成与有源元件接触的电路。 最后，嵌入式有源元件的结构从成型板上释放出来。

公开(公告)号：US07838333B2

公开(公告)日：2010-11-23

申请号：US12611356

申请日：2009-11-03

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

IPC分类号： H01L21/00

CPC分类号： H01L24/97 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/82

摘要： The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

摘要翻译： 本发明公开了一种电子装置封装和封装方法。 具体地，公开了一种适用于具有增强的电气性能和散热效率的无扰动电子器件封装的封装的电子器件封装和方法。 该方法包括：提供具有多个通孔和多个电子器件的衬底; 在所述基板的表面上形成胶合层并将所述电子装置固定在所述胶合层上，其中所述电子装置具有分别与所述通孔对准的I / O单元; 在电子设备之间的间隙中形成多个固定层; 在固定层中分别与通孔对准的多个开口挖沟; 在通孔，开口和基板的表面的一部分上形成多个金属导电单元; 以及在所述衬底的另一表面上形成钝化层。

公开(公告)号：US07754530B2

公开(公告)日：2010-07-13

申请号：US12388191

申请日：2009-02-18

申请人： Enboa Wu ,  Shou-Lung Chen

发明人： Enboa Wu ,  Shou-Lung Chen

IPC分类号： H01L21/44

CPC分类号： H01L24/97 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49568 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2224/83

摘要： A thermal enhanced low profile package structure and a method for fabricating the same are provided. The package structure typically includes a metallization layer with an electronic component thereon which is between two provided dielectric layers. The metallization layer as well as the electronic component is embedded and packaged while the substrates are laminated via a lamination process. The fabricated package structure performs not only a superior electric performance, but also an excellent enhancement in thermal dissipation.

摘要翻译： 提供了一种热增强薄型封装结构及其制造方法。 封装结构通常包括其上具有电子部件的金属化层，其位于两个提供的介电层之间。 金属化层以及电子部件被嵌入和封装，同时通过层压工艺层压基板。 制造的封装结构不仅具有优异的电性能，而且还具有优异的散热增强。

公开(公告)号：US07572676B2

公开(公告)日：2009-08-11

申请号：US11790313

申请日：2007-04-25

申请人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

发明人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

IPC分类号： H01L21/00

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/15321 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/0401

摘要： This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

摘要翻译： 本发明涉及图像传感器模块的封装结构和方法。 该方法包括：提供具有第一图案化导电层的透明基板; 在所述透明基板上承载具有感光有源区域的图像传感器集成电路芯片和至少一个无源芯片，其中所述光敏有源区域面向所述透明基板; 在透明基板上形成绝缘堆积膜; 并且在绝缘堆积膜中形成多个导电通孔，其中导电通孔的端部与透明基板的无源芯片或第一图案化导电层连接，而导电通孔的另一端暴露在表面上 的绝缘堆积膜。 包装方法能够缩小图像传感器模块的结构，简化了处理步骤。

公开(公告)号：US07544529B2

公开(公告)日：2009-06-09

申请号：US11678101

申请日：2007-02-23

申请人： Shou-Lung Chen ,  Fang-Jun Leu ,  Shan-Pu Yu

发明人： Shou-Lung Chen ,  Fang-Jun Leu ,  Shan-Pu Yu

IPC分类号： H01L21/00

CPC分类号： H01L31/0203 ,  H01L23/15 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14683 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.

摘要翻译： 图像传感器模块包括第一基板，设置在第一基板上的第二基板，用于接收与第二基板接合的图像信号倒装芯片的图像传感器装置，以及用于处理来自图像传感器装置的图像信号的半导体器件 嵌入第一衬底。