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    Semiconductor integrated circuitry and method for manufacturing the circuitry
    32.
    发明申请
    Semiconductor integrated circuitry and method for manufacturing the circuitry 有权
    半导体集成电路和制造电路的方法

    公开(公告)号：US20050017274A1

    公开(公告)日：2005-01-27

    申请号：US10920389

    申请日：2004-08-18

    申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

    发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

    IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

    摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

    摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

    Semiconductor integrated circuit device
    36.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06367050B1

    公开(公告)日：2002-04-02

    申请号：US09399229

    申请日：1999-09-20

    申请人： Yasushi Akao ,  Kenichi Kuroda

    发明人： Yasushi Akao ,  Kenichi Kuroda

    IPC分类号： G06F1750

    CPC分类号： G06F15/7814

    摘要： A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.

    摘要翻译： 一种半导体集成电路装置，包括具有非易失性存储器电路的单片微计算机，并且与处理器的周期时间保持高速执行写入和读取操作。 存储器电路的一部分被设置为用于容纳数据处理程序的只读区域，并且其余的存储器用于向其写入和读取数据。 由于不需要优化存储器电路中的ROM和RAM部件的分配，所以单芯片微芯片易于以高生产率进行设计和制造。 根据需要建立程序存储区域，用户比以前更容易使用单片机。

    Method of manufacturing a semiconductor integrated circuit device
    38.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device 有权
    制造半导体集成电路器件的方法

    公开(公告)号：US6069038A

    公开(公告)日：2000-05-30

    申请号：US393623

    申请日：1999-09-10

    申请人： Takashi Hashimoto ,  Kenichi Kuroda ,  Shoji Shukuri

    发明人： Takashi Hashimoto ,  Kenichi Kuroda ,  Shoji Shukuri

    IPC分类号： H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/8244

    CPC分类号： H01L27/10844 ,  H01L21/823425 ,  H01L27/1052 ,  H01L27/10817 ,  H01L27/10873

    摘要： A silicon nitride film is left behind on only regions for forming the gate electrodes (word lines) of memory-cell selecting MISFETs constituting a DRAM, and it is not left behind on either of the gate electrodes of MISFETs constituting a logic LSI and those of MISFETs constituting the memory cells of an SRAM. Thereafter, the gate electrodes (word lines) in the DRAM and the gate electrodes in the logic LSI and the SRAM are simultaneously patterned by etching which employs the silicon nitride film and a photoresist film as a mask. Thus, in the manufacture of a semiconductor integrated circuit device wherein both the DRAM and the logic LSI are mounted, a contact hole forming process (gate-SAC) for the DRAM is made compatible with a contact hole forming process (L-SAC).

    摘要翻译： 仅在形成构成DRAM的存储单元选择MISFET的栅电极（字线）的区域上留下氮化硅膜，并且不留下构成逻辑LSI的MISFET的任一个栅电极， 构成SRAM存储单元的MISFET。 此后，通过采用氮化硅膜和光致抗蚀剂膜作为掩模的蚀刻，同时将DRAM中的栅电极（字线）和逻辑LSI和SRAM中的栅电极图案化。 因此，在其中安装了DRAM和逻辑LSI两者的半导体集成电路器件的制造中，用于DRAM的接触孔形成工艺（gate-SAC）与接触孔形成工艺（L-SAC）兼容。