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    ON-DEMAND ACTIVATION OF MEMORY PATH DURING SLEEP OR ACTIVE MODES
    34.
    发明公开
    ON-DEMAND ACTIVATION OF MEMORY PATH DURING SLEEP OR ACTIVE MODES 审中-公开

    公开(公告)号：US20230376222A1

    公开(公告)日：2023-11-23

    申请号：US17981149

    申请日：2022-11-04

    申请人： Ambiq Micro, Inc.

    发明人： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0625 ,  G06F3/0626 ,  G06F3/0655 ,  G06F3/0673

    摘要： A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

    Memory module with fine-grained voltage adjustment capabilities
    35.
    发明授权
    Memory module with fine-grained voltage adjustment capabilities 有权

    公开(公告)号：US11689204B1

    公开(公告)日：2023-06-27

    申请号：US17894023

    申请日：2022-08-23

    申请人： Ambiq Micro, Inc.

    发明人： Scott Hanson ,  Daniel Martin Cermak

    IPC分类号： H03K19/17784 ,  H03K19/173 ,  H03K19/1776

    CPC分类号： H03K19/17784 ,  H03K19/1737 ,  H03K19/1776

    摘要： Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.

    System for profiling power using ton pulses
    36.
    发明授权
    System for profiling power using ton pulses 有权

    公开(公告)号：US11682967B1

    公开(公告)日：2023-06-20

    申请号：US17877318

    申请日：2022-07-29

    申请人： Ambiq Micro, Inc.

    发明人： Ivan Bogue ,  Jesse Coulon ,  Andre Belanger

    IPC分类号： H02M3/157 ,  G06F1/26 ,  H02M3/158

    CPC分类号： H02M3/157 ,  G06F1/26 ,  H02M3/158

    摘要： A system for determining a power requirement for a device powered by a buck converter on a system on chip based on Time on pulses (Ton) is disclosed. A buck converter supplies output voltage to enable the device. The buck converter is driven by a Ton pulse generator generating Ton pulses to control charging of a load capacitor. A counter counts the Ton pulses during the supply of output voltage while the device is enabled. A controller is coupled to the counter and the buck converter. The controller determines the power requirement for the device based on the count of the Ton pulses. The power requirement may be used to adjust the trim value to change the width of the Ton pulses for greater energy efficiency.

    FLEXIBLE AND LOW POWER CACHE MEMORY ARCHITECTURE
    37.
    发明公开
    FLEXIBLE AND LOW POWER CACHE MEMORY ARCHITECTURE 审中-公开

    公开(公告)号：US20230148253A1

    公开(公告)日：2023-05-11

    申请号：US18053610

    申请日：2022-11-08

    申请人： Ambiq Micro, Inc.

    发明人： Daniel Martin Cermak ,  Stephen James Sheafor

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0625 ,  G06F3/0659 ,  G06F3/0679

    摘要： A low power caching architecture is disclosed. The architecture includes multiple data memory regions, each including a cache memory. The data memory regions are coupled to a peripheral device. A host processor is operable to control power to each of the plurality of data memory regions. The host processor is operable to power on any of data memory regions and power down any unused data memory regions of the data memory regions. A cache control logic is operable to receive a data request from the host processor. The cache control logic requests the data from the peripheral. The host processor powers on at least one of the data memory regions, and stores the requested data in the cache memory of the powered on data memory region.

    On-chip system with context-based energy reduction
    38.
    发明授权
    On-chip system with context-based energy reduction 有权

    公开(公告)号：US11556167B1

    公开(公告)日：2023-01-17

    申请号：US17814832

    申请日：2022-07-25

    申请人： Ambiq Micro, Inc.

    发明人： Carlos Morales

    IPC分类号： G06F1/32 ,  G06F1/3296

    摘要： A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.

    On-demand activation of memory path during sleep or active modes
    39.
    发明授权
    On-demand activation of memory path during sleep or active modes 有权

    公开(公告)号：US11520499B1

    公开(公告)日：2022-12-06

    申请号：US17747410

    申请日：2022-05-18

    申请人： Ambiq Micro, Inc.

    发明人： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

    IPC分类号： G06F3/06

    摘要： A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

    Power efficient context-based audio processing
    40.
    发明授权
    Power efficient context-based audio processing 有权

    公开(公告)号：US11172293B2

    公开(公告)日：2021-11-09

    申请号：US16508062

    申请日：2019-07-10

    申请人： Ambiq Micro, Inc.

    发明人： Arpit Shah ,  Scott McLean Hanson ,  Stephen Howard Nease

    IPC分类号： H04R3/04 ,  G06F3/16 ,  G06F3/01 ,  G06F40/205

    摘要： A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.