公开(公告)号：US5368217A

公开(公告)日：1994-11-29

申请号：US112494

申请日：1993-08-25

Applicant: Richard L. Simmons ,  Michael J. Bertram

Inventor： Richard L. Simmons ,  Michael J. Bertram

IPC: B23K20/02 ,  H01L21/603

CPC classification number: B23K20/02 ,  B23K2201/40 ,  H01L2224/16225

Abstract: A high force flip chip bonding method and system that precisely and forcefully engage a flip chip device with a corresponding wiring pattern on a substrate in a manner that prevents flip chip device and substrate shifting during force application. The method includes the steps of determining the centroid of the pattern formed by the interconnects on the flip chip device. The flip chip device is directed toward the substrate for contacting the corresponding wiring pattern with the interconnects and then the interconnects are compressed into the corresponding wiring pattern using a bonding force. The bonding force is directed along a neutral axis of deflection that is coincident with the centroid. Applying the bonding force along the neutral axis of deflection at the centroid minimizes lateral shifting of the flip chip device relative to the substrate to precisely bond the interconnects to the corresponding wiring pattern.

Abstract translation: 一种大力倒装芯片接合方法和系统，其以在应力施加期间防止倒装芯片器件和衬底移位的方式精确地强制地将倒装芯片器件与衬底上的相应布线图案接合。 该方法包括确定由倒装芯片器件上的互连形成的图案的质心的步骤。 倒装芯片器件被引导到用于使相应布线图案与互连件接触的基板，然后使用结合力将互连件压缩成相应的布线图案。 接合力沿着与质心一致的中立偏转轴线引导。 沿着中心的偏转中性轴施加接合力使倒装芯片器件相对于衬底的横向偏移最小化，以将互连精确地结合到相应的布线图案。

公开(公告)号：US5339391A

公开(公告)日：1994-08-16

申请号：US102021

申请日：1993-08-04

Applicant: David A. Wroblewski ,  William C. Hill ,  Timothy P. McCandless

Inventor： David A. Wroblewski ,  William C. Hill ,  Timothy P. McCandless

IPC: G06F3/033 ,  G06F3/048 ,  G06F17/21 ,  G06F15/62

CPC classification number: G06F17/218 ,  G06F3/04855 ,  Y10S715/973

Abstract: An attribute-enhanced scroll bar is graphically displayed. A selected portion of a stored data file, for example a document, is displayed in a display field, and a scroll bar field including a scroll bar is used to indicate the position of the displayed portion relative to the entire data file. In addition, maps of significant task-specific attributes of the data file, for example particular character strings within a document, are displayed in the scroll bar field of the display along with the scroll bar. The attribute maps indicate the location of the significant attributes within the data file. In addition, the attributes are highlighted within the portion of the data file that is displayed in the display field.

Abstract translation: 以图形方式显示属性增强的滚动条。 所存储的数据文件的选定部分（例如文档）被显示在显示字段中，并且包括滚动条的滚动条字段用于指示所显示的部分相对于整个数据文件的位置。 此外，数据文件的重要任务特定属性（例如文档中的特定字符串）的映射与滚动条一起显示在显示器的滚动条字段中。 属性映射表示数据文件中重要属性的位置。 另外，在显示区域中显示的数据文件的部分内突出显示属性。

公开(公告)号：US5283946A

公开(公告)日：1994-02-08

申请号：US062876

申请日：1993-05-17

Applicant: Richard L. Simmons ,  James D. Wehrly, Jr. ,  Michael J. Bertram

Inventor： Richard L. Simmons ,  James D. Wehrly, Jr. ,  Michael J. Bertram

IPC: H01L21/00 ,  H01L23/495 ,  H01R43/00

CPC classification number: H01L24/50 ,  H01L21/67144 ,  H01L23/49558 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49121 ,  Y10T29/5149 ,  Y10T29/515

Abstract: The excise and lead form of TAB leads bonded to an integrated circuit chip. Leads extending beyond a sidewall are clamped between a first clamp and a form anvil at a first portion spaced from the chip. The leads are also clamped between an excise/form tool and a second clamp at a second portion spaced further from the chip than the first portion. An excise blade cuts the leads outside the second portion. Then the excise/form tool, second clamp and excise blade move downwards in a curved path toward the chip to form a first lead corner against the form anvil and a second lead corner against the excise/form tool without splaying or galling the leads.

Abstract translation: TAB引脚的切割和引线形式引线结合到集成电路芯片。 延伸超过侧壁的引线在与芯片间隔开的第一部分处夹在第一夹具和砧座之间。 在比第一部分更远离芯片的第二部分处，引线也夹在消费/成型工具和第二夹具之间。 切割刀将第二部分之外的引线切割。 然后，切割/成形工具，第二夹具和切割刀片以弯曲的路径向下移动朝向芯片，以形成抵抗砧座的第一引导角和抵靠消费/形成工具的第二引导角，而不会使引线绷直或磨损。

公开(公告)号：US5225157A

公开(公告)日：1993-07-06

申请号：US701543

申请日：1991-05-16

Applicant: Colin A. McKay

Inventor： Colin A. McKay

IPC: B23K35/26 ,  C22C28/00 ,  H05K3/34

CPC classification number: C22C28/00 ,  B23K35/26 ,  H05K3/3457

Abstract: An amalgam and a method of preparing an amalgam for bonding two articles together, which includes mixing a composition of a liquid metal and a metal powder to thoroughly wet the metal powder with the liquid metal, and thereafter mixing a composition with a pestle element for mechanically amalgamating the composition. Other additives may be provided such as ductile metals, additives containing oxides, ceramics, or other non-metallic compounds, and volatile constituents. The amalgamated composition can then wet surfaces to be bonded and harden at or near room temperature.

Abstract translation: 一种汞合金和一种制备用于将两个物品结合在一起的汞齐的方法，其包括将液态金属和金属粉末的组合物混合以用液态金属彻底润湿金属粉末，然后将组合物与用于机械的研杵元件混合 合并组合物。 可以提供其它添加剂，例如延性金属，含氧化物的添加剂，陶瓷或其它非金属化合物以及挥发性成分。 然后合并的组合物可以在室温或接近室温的情况下将表面粘合并硬化。

公开(公告)号：US5178743A

公开(公告)日：1993-01-12

申请号：US649311

申请日：1991-01-30

Applicant: Nalin Kumar

Inventor： Nalin Kumar

IPC: C23C14/34 ,  C23C14/56 ,  H01J37/34 ,  H01L39/24

CPC classification number: H01J37/3402 ,  C23C14/3407 ,  C23C14/56 ,  H01J37/3277 ,  H01J37/342

Abstract: A system for depositing a film on a substrate includes a sputtering system and means for causing the substrate to move through the sputtering system. Embodiments of the present invention employ a cylindrical hollow cathode magnetron sputtering system, which causes the overall film deposition system to be ideally suited for coating elongate cylindrical substrates such as wires and fibers and the like.

Abstract translation: 用于在衬底上沉积膜的系统包括溅射系统​​和用于使衬底移动通过溅射系统的装置。 本发明的实施例采用圆柱形空心阴极磁控溅射系统，其使得整个膜沉积系统理想地适用于涂覆细长的圆柱形基底，例如电线和纤维等。

公开(公告)号：US5173442A

公开(公告)日：1992-12-22

申请号：US857011

申请日：1992-03-24

Applicant: David H. Carey

Inventor： David H. Carey

IPC: H01L21/311 ,  H01L21/48 ,  H01L21/768 ,  H01L23/485 ,  H05K3/00 ,  H05K3/10 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L21/76817 ,  H01L21/31144 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/485 ,  H05K3/0032 ,  H05K3/0041 ,  H05K3/005 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/0166 ,  H05K2201/09563 ,  H05K2203/0108 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/107 ,  H05K2203/1189 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/422 ,  H05K3/4644 ,  H05K3/4661 ,  Y10S438/94

Abstract: Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

Abstract translation: 可以在相对较少的步骤中以低成本的蚀刻和图案化技术形成通过部分延伸的通孔和完全延伸穿过例如基板或集成电路的电互连中的绝缘层的通孔。 然后可以以相对较少的步骤在通道和通孔中填充电导体。 在一个实施例中，将通孔和通道暴露的不可侵蚀的硬掩模放置在聚酰亚胺层上，暴露通孔但覆盖通道的可侵蚀的软掩模放置在硬掩模上，并施加等离子体蚀刻。 蚀刻通孔区域直到软掩模完全侵蚀，然后蚀刻通孔区和通道区，以提供部分蚀刻的通道和完全蚀刻的通孔。 此后，种子层沉积在互连上，并且导电层电解沉积在种子层上，基本上填充通道和通孔。 然后通过抛光将互连表面平坦化，直到电导体仅保留在通道和通孔中。

公开(公告)号：US5164332A

公开(公告)日：1992-11-17

申请号：US669814

申请日：1991-03-15

Applicant: Nalin Kumar

Inventor： Nalin Kumar

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L23/5283 ,  H01L23/53233 ,  H01L2924/0002

Abstract: A diffusion barrier which reduces the diffusion of a copper feature into an oxygen containing polymer is provided by a copper metal alloy. The diffusion barrier is fabricated by coating a metal on a copper feature, heating the metal and copper feature to form an alloy of the copper feature and the metal, etching the non-alloyed metal which covers the alloy, and depositing an oxygen containing polymer on the alloy. Preferably the metal is aluminum and a copper aluminum alloy diffusion barrier is at least 300 angstroms thick and contains at least 8 percent aluminum on the surface in contact with the polymer.

Abstract translation: 通过铜金属合金提供减少铜特征扩散到含氧聚合物中的扩散阻挡层。 通过在铜特征上涂覆金属来制造扩散阻挡层，加热金属和铜的特征以形成铜特征和金属的合金，蚀刻覆盖合金的非合金金属，并将含氧聚合物沉积在 合金。 优选地，金属是铝，并且铜铝合金扩散阻挡层至少为300埃厚，并且在与聚合物接触的表面上含有至少8％的铝。

公开(公告)号：US5156997A

公开(公告)日：1992-10-20

申请号：US653609

申请日：1991-02-11

Applicant: Nalin Kumar ,  Rama R. Goruganthu ,  Mohammed K. Ghazi

Inventor： Nalin Kumar ,  Rama R. Goruganthu ,  Mohammed K. Ghazi

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01J2201/30457 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H05K2201/2081 ,  H05K2203/0554 ,  H05K2203/107 ,  H05K3/0023 ,  H05K3/0041

Abstract: A method of making bonding bumps on the pads of an electrical chip including depositing a layer of metallic adhesion material over the surface, depositing metallic bumps on the metallic adhesion material over each of the pad areas using a focused liquid metal ion source, and chemically etching the layer of metallic adhesion material off the surface outside of the deposited bumps.

Abstract translation: 一种在电芯片的焊盘上形成接合凸块的方法，包括在表面上沉积一层金属粘附材料，使用聚焦的液态金属离子源在每个焊盘区域上沉积金属粘附材料上的金属凸块，以及化学蚀刻 金属粘合材料层从沉积的凸块外部的表面离开。

公开(公告)号：US5132873A

公开(公告)日：1992-07-21

申请号：US663062

申请日：1991-02-28

Applicant: Richard D. Nelson ,  Omkarnath R. Gupta ,  Dennis J. Herrell

Inventor： Richard D. Nelson ,  Omkarnath R. Gupta ,  Dennis J. Herrell

IPC: H01L23/40 ,  H05K7/20

CPC classification number: H01L23/4093 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: An article provides sealing of an electronic component connected to a mating fluid heat exchanger by providing a diaphragm with an opening shaped to fit about the heat exchanger, the opening forming a sealing lip. A clamping ring, which expands and contracts as a function of temperature is placed around the lip of the diaphragm and subject to a temperature to shrink the clamping ring against the lip and heat exchanger for sealing the diaphragm thereto. Preferably the clamping ring is a shape memory alloy metal. In addition, a compressible metal seal may be placed between the lip and the heat exchanger to increase the ability to seal.

Abstract translation: 一种制品通过提供具有开口形状的隔膜来提供连接到配合流体热交换器的电子部件的密封，所述隔膜的形状适于围绕热交换器，所述开口形成密封唇。 将围绕温度膨胀和收缩的夹紧环放置在隔膜的唇缘周围，并承受一定的温度，以将夹紧环收缩在唇缘和热交换器上，以将隔膜密封。 优选地，夹紧环是形状记忆合金金属。 此外，可压缩金属密封件可以放置在唇缘和热交换器之间以增加密封能力。

公开(公告)号：US5122753A

公开(公告)日：1992-06-16

申请号：US631111

申请日：1990-12-20

Applicant: Thomas K. Myers ,  John D. Ferguson

Inventor： Thomas K. Myers ,  John D. Ferguson

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/305

CPC classification number: G01R31/025 ,  G01R31/2853 ,  G01R31/305

Abstract: A method of testing electrical circuits on a substrate for detecting shorts and opens. A plurality of electrical networks in which each network has one or more nodes are tested by selectively electrically charging certain nodes and selectively testing other nodes for detecting shorts and opens between the nodes. The method of testing allows various levels of testing to be performed for detecting more and greater different kinds of possible defects.

Abstract translation: 一种在基板上测试电路以检测短路和断开的方法。 每个网络具有一个或多个节点的多个电网络通过选择性地对某些节点进行充电来进行测试，并选择性地测试其他节点以检测短路并在节点之间打开。 测试方法允许执行各种级别的测试以检测越来越多的不同种类的可能的缺陷。