中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

188 records (took 0.02 seconds)

    Semiconductor accelerometer and method of its manufacture
    31.
    发明授权
    Semiconductor accelerometer and method of its manufacture 失效
    半导体加速度计及其制造方法

    公开(公告)号：US5429993A

    公开(公告)日：1995-07-04

    申请号：US216217

    申请日：1994-03-21

    Applicant: Bruce A. Beitman

    Inventor： Bruce A. Beitman

    IPC: G01P15/12 ,  B81B3/00 ,  G01P15/08 ,  H01L21/306 ,  H01L29/84 ,  H01L21/308

    CPC classification number: B81C1/0015 ,  G01P15/0802 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81C2201/0104 ,  B81C2201/0136 ,  B81C2201/019 ,  B81C2201/0191 ,  G01P2015/0828

    Abstract: A semiconductor accelerometer is formed by attaching a semiconductor layer to a handle wafer by a thick oxide layer. Accelerometer geometry is patterned in the semiconductor layer, which is then used as a mask to etch out a cavity in the underlying thick oxide. The mask may include one or more apertures, so that a mass region will have corresponding apertures to the underlying oxide layer. The structure resulting from an oxide etch has the intended accelerometer geometry of a large volume mass region supported in cantilever fashion by a plurality of piezo-resistive arm regions to a surrounding, supporting portion of the semiconductor layer. Directly beneath this accelerometer geometry is a flex-accommodating cavity realized by the removal of the underlying oxide layer. The semiconductor layer remains attached to the handle wafer by means of the thick oxide layer that surrounds the accelerometer geometry, and which was adequately masked by the surrounding portion of the top semiconductor layer during the oxide etch step. In a second embodiment support arm regions are dimensioned separately from the mass region, using a plurality of buried oxide regions as semiconductor etch stops.

    Abstract translation: 半导体加速度计是通过用厚的氧化物层将半导体层附着在手柄晶片上形成的。 加速度传感器几何形状在半导体层中图案化，然后将其用作掩模以蚀刻下面的厚氧化物中的空腔。 掩模可以包括一个或多个孔，使得质量区域将具有到下面的氧化物层的对应的孔。 由氧化物蚀刻产生的结构具有通过多个压阻臂区域以半悬臂方式支撑到半导体层的周围的支撑部分的大体积质量区域的预期加速度计几何形状。 直接在该加速度计几何形状之下的是通过去除下面的氧化物层而实现的柔性容纳腔。 半导体层通过围绕加速度计几何形状的厚氧化物层保持附着到处理晶片，并且在氧化物蚀刻步骤期间，半导体层被顶部半导体层的周围部分充分掩蔽。 在第二实施例中，使用多个掩埋氧化物区域作为半导体蚀刻停止件，将支撑臂区域与质量区域分开设计。

    Nucleation control of diamond films by microlithographic patterning
    32.
    发明授权
    Nucleation control of diamond films by microlithographic patterning 失效
    通过微光刻图案对金刚石膜的成核控制

    公开(公告)号：US5242711A

    公开(公告)日：1993-09-07

    申请号：US746458

    申请日：1991-08-16

    Applicant: Jeffrey D. DeNatale ,  John F. Flintoff ,  Alan B. Harker ,  Patrick J. Hood ,  Gerald D. Robinson

    Inventor： Jeffrey D. DeNatale ,  John F. Flintoff ,  Alan B. Harker ,  Patrick J. Hood ,  Gerald D. Robinson

    IPC: B81B3/00 ,  B81C99/00 ,  C23C16/02 ,  C23C16/27 ,  G02B1/11 ,  G03F7/00

    CPC classification number: G02B1/118 ,  B81C1/00111 ,  B81C1/00198 ,  B81C1/0038 ,  C23C16/0227 ,  C23C16/0272 ,  C23C16/274 ,  C23C16/277 ,  G03F7/00 ,  B81B2201/035 ,  B81B2201/047 ,  B81C2201/0191 ,  B81C2201/056 ,  Y10T428/30

    Abstract: A high temperature resist process is combined with microlithographic patterning for the production of materials, such as diamond films, that require a high temperature deposition environment. A conventional polymeric resist process may be used to deposit a pattern of high temperature resist material. With the high temperature resist in place and the polymeric resist removed, a high temperature deposition process may proceed without degradation of the resist pattern. After a desired film of material has been deposited, the high temperature resist is removed to leave the film in the pattern defined by the resist. For diamond films, a high temperature silicon nitride resist can be used for microlithographic patterning of a silicon substrate to provide a uniform distribution of diamond nucleation sites and to improve diamond film adhesion to the substrate. A fine-grained nucleation geometry, established at the nucleation sites, is maintained as the diamond film is deposited over the entire substrate after the silicon nitride resist is removed. The process can be extended to form microstructures of fine-grained polycrystalline diamond, such as rotatable microgears and surface relief patterns, that have the desirable characteristics of hardness, wear resistance, thermal conductivity, chemical inertness, anti-reflectance, and a low coefficient of friction.

    Abstract translation: 将高温抗蚀剂工艺与用于生产需要高温沉积环境的材料（例如金刚石膜）的微光刻图案组合。 传统的聚合物抗蚀剂工艺可用于沉积耐高温材料的图案。 通过将高温抗蚀剂置于适当位置并除去聚合物抗蚀剂，可以进行高温沉积工艺而不降解抗蚀剂图案。 在已经沉积所需的材料膜之后，去除高温抗蚀剂以使膜以由抗蚀剂限定的图案离开。 对于金刚石膜，可以使用高温氮化硅抗蚀剂用于硅衬底的微光刻图案以提供金刚石成核位点的均匀分布并且改善金刚石膜对衬底的粘附。 在去除氮化硅抗蚀剂之后，在整个衬底上沉积金刚石膜，保持在成核位置建立的细晶粒成核几何形状。 该方法可以扩展以形成具有期望的硬度，耐磨性，导热性，化学惰性，抗反射性和低系数的细晶粒多晶金刚石的微观结构，例如可旋转的微观尺寸和表面浮雕图案 摩擦。

    Method for manufacturing a hermetically sealed structure
    34.
    发明授权
    Method for manufacturing a hermetically sealed structure 有权
    密封结构的制造方法

    公开(公告)号：US09051172B2

    公开(公告)日：2015-06-09

    申请号：US13639423

    申请日：2011-04-15

    Applicant: Gjermund Kittilsland ,  Daniel Lapadatu ,  Sissel Jacobsen ,  Trond Westgaard

    Inventor： Gjermund Kittilsland ,  Daniel Lapadatu ,  Sissel Jacobsen ,  Trond Westgaard

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00269 ,  B81B7/0032 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C2201/019 ,  B81C2201/0191 ,  B81C2203/0118 ,  B81C2203/031 ,  B81C2203/058

    Abstract: A method for providing hermetic sealing within a silicon-insulator composite wafer for manufacturing a hermetically sealed structure, comprising the steps of: patterning a first silicon wafer to have one or more recesses that extend at least partially through the first silicon wafer; filling said recesses with an insulator material able to be anodically bonded to silicon to form a first composite wafer having a plurality of silicon-insulator interfaces and a first contacting surface consisting of insulator material; and using an anodic bonding technique on the first contacting surface and an opposing second contacting surface to create hermetic sealing between the silicon-insulator interfaces, wherein the second contacting surface consists of silicon.

    Abstract translation: 一种用于在用于制造密封结构的硅绝缘体复合晶片内提供气密密封的方法，包括以下步骤：将第一硅晶片图案化成具有至少部分延伸穿过第一硅晶片的一个或多个凹槽; 用能够与硅阳极结合的绝缘体材料填充所述凹槽，以形成具有多个硅 - 绝缘体界面的第一复合晶片和由绝缘体材料组成的第一接触表面; 以及在所述第一接触表面和相对的第二接触表面上使用阳极接合技术以在所述硅 - 绝缘体界面之间形成气密密封，其中所述第二接触表面由硅组成。

    NANO PATTERN FORMATION
    39.
    发明申请
    NANO PATTERN FORMATION 有权
    纳米图案形成

    公开(公告)号：US20110020608A1

    公开(公告)日：2011-01-27

    申请号：US12507718

    申请日：2009-07-22

    Applicant: Kwangyeol LEE

    Inventor： Kwangyeol LEE

    IPC: B32B3/02 ,  B05D3/02 ,  B05D1/32

    CPC classification number: B81C1/00031 ,  B81C1/00373 ,  B81C2201/0149 ,  B81C2201/0191 ,  Y10T428/24612 ,  Y10T428/24802

    Abstract: Nano structure patterning formation includes coating a part of a structural guide with a hydrophobic polymer, positioning the structural guide on a substrate, coating at least a part of the substrate with a film made of a block copolymer, and annealing the film made of the block copolymer to align the block copolymer.

    Abstract translation: 纳米结构图案形成包括用疏水聚合物涂覆结构导向器的一部分，将结构引导件定位在基底上，用由嵌段共聚物制成的膜涂覆至少一部分基底，并且将由该块制成的膜退火 共聚物以对齐嵌段共聚物。

Patent Agency Ranking