公开(公告)号：US07016198B2

公开(公告)日：2006-03-21

申请号：US10408951

申请日：2003-04-08

申请人： John Thomas Fessler ,  Keith Bryan Hardin ,  Eric Wayne Westerfield

发明人： John Thomas Fessler ,  Keith Bryan Hardin ,  Eric Wayne Westerfield

IPC分类号： H05K7/06 ,  H05K9/00

CPC分类号： H05K1/0218 ,  H05K1/0231 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/09772 ,  H05K2201/10689

摘要： A multi-layer printed circuit board (PCB) routes signal traces on internal signal layer(s) and includes power planes on the two outermost layers. The outer layers are maintained at the same non-ground voltage level, and are electrically connected by a series of vias that circumscribe signal traces on the internal layer(s). With a preferred maximum spacing of one-tenth the wavelength of electromagnetic energy generated by the signal traces, the vias, together with the outer power planes, contain electromagnetic energy within the PCB. One or more of the outer planes may include a second power plane area maintained at a different voltage. The two power plane areas are connected by decoupling capacitors, located proximate underlying signal traces that traverse the two power plane areas.

摘要翻译： 多层印刷电路板（PCB）在内部信号层上传送信号迹线，并且包括两个最外层的电源层。 外层保持在相同的非接地电压电平，并且通过一系列通孔来电连接，这些通孔围绕内层上的信号迹线。 通过由信号迹线产生的电磁能量波长的十分之一的优选最大间距，通孔与外部电源平面在PCB内包含电磁能。 一个或多个外平面可以包括维持在不同电压的第二电源平面区域。 两个电力平面区域通过去耦电容器连接，位于邻近穿过两个电源平面区域的底层信号迹线。

公开(公告)号：US20050047032A1

公开(公告)日：2005-03-03

申请号：US10928172

申请日：2004-08-30

申请人： Mitsuhiro Kanayama ,  Toru Itabashi

发明人： Mitsuhiro Kanayama ,  Toru Itabashi

IPC分类号： H02M3/00 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H02H7/00

CPC分类号： H02M3/00 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10166

摘要： An electronic control apparatus includes an exclusive power source wiring for a charge pump circuit which is discriminated from a common power source wiring. The exclusive power source wiring is connected to the common power source wiring via a via-hole va having the impedance larger than that of the wiring pattern. Similarly, the electronic control apparatus includes an exclusive ground wiring for the charge pump circuit which is discriminated from a common ground wiring. The exclusive ground wiring is connected to the common ground via an additional via-hole vb. Furthermore, a noise-suppressing capacitor C is connected between a power source wiring and a ground wiring. The power source wiring interposes between the via-hole va and the exclusive power source wiring, and the ground wiring interposes between the via-hole vb and the exclusive ground wiring.

摘要翻译： 电子控制装置包括用于与公共电源布线区分开的用于电荷泵电路的专用电源布线。 专用电源布线经由具有比布线图案的阻抗大的阻抗的通孔va连接到公共电源布线。 类似地，电子控制装置包括用于与公共接地布线区分开的用于电荷泵电路的专用接地布线。 专用接地线通过附加的通孔vb连接到公共地。 此外，噪声抑制电容器C连接在电源布线和接地布线之间。 通孔va和专用电源布线之间的电源布线插入，并且接地布线插入通孔vb和专用接地布线之间。

公开(公告)号：US20040251534A1

公开(公告)日：2004-12-16

申请号：US10710731

申请日：2004-07-30

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/119 ,  H01L031/113 ,  H01L023/52

CPC分类号： H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

摘要： A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

摘要翻译： 支持两种不同包装技术的中央处理单元（CPU）的布局结构，包括包括布局结构和布局方法的主板。 根据本发明的优选实施例的布局结构从上到下顺序地在CPU的信号区域中放置顶层信号层，接地层，具有接地电位的功率层和底部焊料层 耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。 因此，耦合到控制芯片的CPU的部分信号可以放置在底部焊料层上。 由于本发明的优选实施例在布局设计中提供了更多的灵活性，因此可以在四层堆栈结构的主板上设计支持不同封装技术的Pentium IV CPU的布局结构，并且这两个CPU可以被 相同的控制芯片。

公开(公告)号：US06800814B2

公开(公告)日：2004-10-05

申请号：US10046163

申请日：2002-01-16

申请人： Tohru Ohsaka

发明人： Tohru Ohsaka

IPC分类号： H05K103

CPC分类号： H05K1/0216 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09354

摘要： A multi-layered printed wiring board capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.

摘要翻译： 一种多层印刷电路板，即使在布线层数量减少并且减少辐射噪声的情况下也能够确保所需的布线密度。 多层印刷电路板具有至少三个布线层，每个布线层至少具有至少一个电源线或接地线，并且另一种线，所述布线层各自具有外边缘。 在至少一个布线层的外边缘处形成接地线。 在地线内形成基本电源线。 至少一条电源线从基本电源线延伸。 多个电子部件安装在至少一个布线层上。 所述至少一个电源线经由所述布线层中的至少一个布线到所述电子部件的安装位置。

公开(公告)号：US06793502B2

公开(公告)日：2004-09-21

申请号：US09957047

申请日：2001-09-20

申请人： Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

发明人： Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

IPC分类号： H01R1200

CPC分类号： H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

摘要： An electrical connector for use in a power module includes a first end portion for forming an electrical connection with a substrate, a second end portion, and a compliant portion situated between the first end portion and the second end portion. The compliant portion includes a compressed position and a decompressed position. The first end portion is configured for forming an electrical connection with a substrate if the compliant portion is in the compressed position.

摘要翻译： 用于功率模块的电连接器包括用于与衬底形成电连接的第一端部，第二端部和位于第一端部和第二端部之间的柔性部分。 柔顺部分包括压缩位置和解压缩位置。 如果柔性部分处于压缩位置，则第一端部构造成用于与基底形成电连接。

公开(公告)号：US06636429B2

公开(公告)日：2003-10-21

申请号：US09957001

申请日：2001-09-20

申请人： Douglas Maly ,  Sayeed Ahmed ,  Scott Parkhill ,  Fred Flett

发明人： Douglas Maly ,  Sayeed Ahmed ,  Scott Parkhill ,  Fred Flett

IPC分类号： H05K900

CPC分类号： H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

摘要： A high frequency, low impedance network is integrated into the substrate level of a power module for the reduction of electromagnetic interference (“EMI”). In one embodiment, capacitance is electrically connected to at least one of the positive conducting layer in a substrate or the negative conducting layer in a substrate and a ground. Integrating a capacitive network of low stray inductance in a substrate of a power module allows relatively small, inexpensive capacitors to be used.

公开(公告)号：US20020108779A1

公开(公告)日：2002-08-15

申请号：US10046163

申请日：2002-01-16

发明人： Tohru Ohsaka

IPC分类号： H05K001/11

CPC分类号： H05K1/0216 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09354

摘要： A multi-layered printed wiring board is provided that is capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.

摘要翻译： 提供了一种多层印刷电路板，即使在布线层数量减少并且减少辐射噪声的情况下也能够确保所需的配线密度。 多层印刷电路板具有至少三个布线层，每个布线层至少具有至少一个电源线或接地线，并且另一种线，所述布线层各自具有外边缘。 在至少一个布线层的外边缘处形成接地线。 在地线内形成基本电源线。 至少一条电源线从基本电源线延伸。 多个电子部件安装在至少一个布线层上。 所述至少一个电源线经由所述布线层中的至少一个布线到所述电子部件的安装位置。

公开(公告)号：US20020040811A1

公开(公告)日：2002-04-11

申请号：US10005464

申请日：2001-12-03

发明人： Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

IPC分类号： H05K001/16 ,  H05K001/00 ,  H01R012/00

CPC分类号： H05K1/141 ,  G06F1/189 ,  H05K1/0263 ,  H05K3/325 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09345 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144

摘要： A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.

摘要翻译： 用于向处理器传送电力的系统使得DC-DC转换器基板能够在Z轴方向上固定到处理器载体。 与转换器以大致平行于母板表面的方向插入处理器载体的系统相比，以这种方式将转换器组装到处理器的能力便于组装。

公开(公告)号：US6040530A

公开(公告)日：2000-03-21

申请号：US986078

申请日：1997-12-05

申请人： Robert J. Wharton ,  Eric R. Daniel ,  Joseph D. Brown

发明人： Robert J. Wharton ,  Eric R. Daniel ,  Joseph D. Brown

IPC分类号： G01R31/02 ,  G01R31/316 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K13/08 ,  H01R9/09

CPC分类号： G01R31/316 ,  H05K1/0268 ,  H05K1/111 ,  H05K13/08 ,  H05K2201/0761 ,  H05K2201/09345 ,  H05K2201/09772 ,  H05K2201/10106 ,  H05K2201/10734 ,  H05K3/3436 ,  Y02P70/611

摘要： A printed circuit board can be used as a test card. The printed circuit board has a first image and a second image. The first image includes a first array pattern for attaching a package, a first power plane, and a first ground plane. The second image includes a second array pattern for attaching a package, a second power plane, and a second ground plane. A first routing area between the first image and the second image electrically and physically isolates the first power plane from the second power plane. The first routing area also physically isolates the first ground plane from the second ground plane. A first single trace extends through the first routing area. The first single trace electrically connects the first ground plane to the second ground plane.

摘要翻译： 印刷电路板可用作测试卡。 印刷电路板具有第一图像和第二图像。 第一图像包括用于附接封装的第一阵列图案，第一电源平面和第一接地平面。 第二图像包括用于附接封装的第二阵列图案，第二电源平面和第二接地平面。 第一图像和第二图像之间的第一路由区域电和物理地隔离第一电力平面与第二电力平面。 第一布线区域还将第一接地平面与第二接地平面物理隔离。 第一个单一轨迹延伸穿过第一个路线区域。 第一单个迹线将第一接地平面电连接到第二接地平面。

公开(公告)号：US5336855A

公开(公告)日：1994-08-09

申请号：US817238

申请日：1992-01-06

申请人： Joachim Kahlert ,  Klaus P. May ,  Joachim Noll

发明人： Joachim Kahlert ,  Klaus P. May ,  Joachim Noll

IPC分类号： H05K3/46 ,  H05K1/02 ,  H05K1/00

CPC分类号： H05K1/0253 ,  H05K1/0219 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/0969

摘要： The invention relates to a multilayer printed circuit board, in particular, for high-frequency operation, having least an outer, plane dielectric layer for accommodating interconnection paths of equal cross-section and component as well as further alternately provided metallic and dielectric layers for forming a reference earth and for the voltage supply to said interconnection paths and components via plated-through holes. In order to obtain a plane surface for the interconnection paths and predetermined areas on the printed circuit board, which areas have different characteristic impedances when interconnection paths having the same cross-section are used, at least the first metal layer comprises at least one window and the subsequent metal layer has a metal island corresponding to the area of the window, which island is connected to the reference earth via a buried plated-through hole, and the characteristic impedance of the interconnection paths is a function of the resulting thickness of the effective dielectric layers the number of which is increased in the area of the window.

摘要翻译： 本发明涉及一种多层印刷电路板，特别是用于高频操作的多层印刷电路板，具有至少一个用于容纳相等横截面和分量的互连路径的外平面介电层，以及进一步交替提供用于形成的金属和电介质层 参考地和用于通过电镀通孔对所述互连路径和部件的电压供应。 为了获得互连路径和印刷电路板上的预定区域的平面，当使用具有相同横截面的互连路径时，哪些区域具有不同的特性阻抗，至少第一金属层包括至少一个窗口和 随后的金属层具有对应于窗口区域的金属岛，该岛通过掩埋电镀通孔连接到参考地，并且互连路径的特征阻抗是所产生的有效的厚度的函数 电介质层的数量在窗口的面积上增加。