公开(公告)号：US12094829B2

公开(公告)日：2024-09-17

申请号：US17384796

申请日：2021-07-25

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/538 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L27/0688

Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the second level includes at least one voltage regulator.

公开(公告)号：US20240297169A1

公开(公告)日：2024-09-05

申请号：US18662468

申请日：2024-05-13

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L27/06

CPC classification number: H01L27/0688

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; at least four electronic circuit units (ECUs); a redundancy circuit, where each of the at least four ECUs includes a first circuit, which includes a portion of the first transistors, where each of the at least four ECUs includes a second circuit, the second circuit including some second transistors, where each of the at least four ECUs includes a vertical connectivity structure which includes pillars, where the pillars provide electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide and metal to metal bonding regions.

公开(公告)号：US12041792B1

公开(公告)日：2024-07-16

申请号：US18605401

申请日：2024-03-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H10B80/00 ,  G11C16/28 ,  H01L23/00 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B51/20 ,  G11C16/14

CPC classification number: H10B80/00 ,  G11C16/28 ,  H01L24/08 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B51/20 ,  G11C16/14 ,  H01L2224/08145

Abstract: A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

公开(公告)号：US20240224545A1

公开(公告)日：2024-07-04

申请号：US18605401

申请日：2024-03-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H10B80/00 ,  G11C16/14 ,  G11C16/28 ,  H01L23/00 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B51/20

CPC classification number: H10B80/00 ,  G11C16/28 ,  H01L24/08 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B51/20 ,  G11C16/14 ,  H01L2224/08145

Abstract: A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

公开(公告)号：US20240179915A1

公开(公告)日：2024-05-30

申请号：US18515255

申请日：2023-11-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B43/27 ,  H01L23/528 ,  H01L27/02 ,  H01L29/167 ,  H01L29/47 ,  H01L29/78 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B53/20

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B53/20

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one digital to analog converter circuit.

公开(公告)号：US20240178040A1

公开(公告)日：2024-05-30

申请号：US18389577

申请日：2023-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

公开(公告)号：US20240170319A1

公开(公告)日：2024-05-23

申请号：US18542757

申请日：2023-12-17

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: 3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer, a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells, a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer, a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, different write voltages for different dies.

公开(公告)号：US11990462B2

公开(公告)日：2024-05-21

申请号：US18384883

申请日：2023-10-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/18 ,  H01L21/28 ,  H01L21/324 ,  H01L23/48 ,  H01L25/065 ,  H01L27/02 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L25/18 ,  H01L21/28194 ,  H01L21/324 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/0266 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785 ,  H01L2225/06541

Abstract: A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; parts of the second transistors are made with Atomic Layer Deposition (“ALD”); the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.

公开(公告)号：US11984438B2

公开(公告)日：2024-05-14

申请号：US18388848

申请日：2023-11-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L25/16 ,  H01L23/528 ,  H01L25/075 ,  H01L33/32

CPC classification number: H01L25/167 ,  H01L23/5283 ,  H01L25/0753 ,  H01L33/32

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including at least one electromagnetic wave receiver, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US11978731B2

公开(公告)日：2024-05-07

申请号：US16797231

申请日：2020-02-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L25/00 ,  H01L25/065 ,  H10B20/00 ,  H10B20/20 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10N70/00

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H10B20/20 ,  H10B20/65 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B63/84 ,  H10N70/011

Abstract: A method to process a 3D device, the method including: providing a first substrate including a first level including a first single crystal silicon layer and a plurality of first transistors; providing a second substrate including a second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer; forming a plurality of third transistors including the third single crystal silicon layer; forming a plurality of metal layers interconnecting the plurality of third transistors; and then performing a hybrid bonding of the second level onto the first level.