公开(公告)号：US20170033000A1

公开(公告)日：2017-02-02

申请号：US14810143

申请日：2015-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie ,  Peng Xu

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/60 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78

Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

公开(公告)号：US09558995B2

公开(公告)日：2017-01-31

申请号：US14750741

申请日：2015-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

Abstract translation: 用于填充结构之间的间隙的方法包括通过间隙形成彼此相邻的多个高纵横比结构，在结构的顶部上形成第一介电层，并在结构上共形沉积间隔电介质层。 间隔电介质层从水平表面去除，保护层共形沉积在结构上。 间隙填充有可流动电介质，其通过选择性蚀刻工艺凹陷到结构侧壁的高度，使得保护层保护结构侧壁上的间隔电介质层。 使用比保护层更高的蚀刻电阻将第一介电层和间隔电介质层暴露在高度之上，以通过蚀刻工艺保持间隔层电介质的尺寸。 间隙由高密度等离子体填充物填充。

公开(公告)号：US09536982B1

公开(公告)日：2017-01-03

申请号：US14930895

申请日：2015-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L29/51 ,  H01L21/31 ,  H01L29/78 ,  H01L29/423 ,  H01L21/283 ,  H01L21/768 ,  H01L23/522 ,  H01L21/764 ,  H01L21/8238

CPC classification number: H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

Abstract translation: 一种在半导体器件的沟道区上包括栅极结构的半导体器件。 源极和漏极区域可以存在于沟道区域的相对侧上。 半导体器件还可以包括存在于栅极结构的侧壁上的复合栅极侧壁间隔物。 复合栅极侧壁间隔物可以包括其中封装有气隙的第一组合物部分和完全固体并存在于第一组合物部分顶部的第二组合物部分。

公开(公告)号：US09536750B1

公开(公告)日：2017-01-03

申请号：US14870932

申请日：2015-09-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0692

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

Abstract translation: 制造半导体器件的方法包括在衬底上设置第一硬掩模（HM），非晶硅和第二HM; 在第二HM上设置氧化物和中性层; 去除所述氧化物和中性层的一部分以暴露所述第二HM的一部分; 通过选择性地回填聚合物形成引导图案; 在引导图案上形成自组装嵌段共聚物（BCP）; 去除BCP的一部分以形成蚀刻模板; 将图案从所述模板转移到衬底中并且形成具有不同材料和高度的两种类型的HM堆叠的均匀硅片阵列; 填充氧化物，然后平坦化; 用第三HM材料选择性地去除和更换较高的HM堆叠; 平坦化表面并暴露两个HM堆叠; 并选择性地去除下面的较短的HM堆叠和硅片。

公开(公告)号：US20160372332A1

公开(公告)日：2016-12-22

申请号：US15240554

申请日：2016-08-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc

Inventor： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

公开(公告)号：US09502286B2

公开(公告)日：2016-11-22

申请号：US14674460

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/283 ,  H01L29/66 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

公开(公告)号：US09496354B2

公开(公告)日：2016-11-15

申请号：US14812150

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Andreas Knorr ,  Christopher Prindle

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/311 ,  H01L21/285 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/41758 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Abstract translation: 本文公开的一种示例性方法包括去除侧壁间隔件和栅极盖层，从而暴露牺牲栅极结构的上表面和侧壁，在器件的源极/漏极区域上方以及在侧壁和上部上形成蚀刻停止层 牺牲栅极结构的表面，在蚀刻停止层上方形成第一绝缘材料层，去除牺牲栅极结构，以便限定由蚀刻停止层的部分横向限定的替代栅极腔，形成替代栅极结构 并且在替换栅极结构上方形成第二栅极盖层。

公开(公告)号：US09478538B1

公开(公告)日：2016-10-25

申请号：US14820661

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/283

CPC classification number: H01L27/088 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

Abstract translation: 一种方法包括形成第一和第二栅极腔以暴露半导体材料的第一和第二部分。 栅极绝缘层形成在第一和第二栅极腔中。 第一工作功能材料层形成在第一浇口腔中。 第二工作功能材料层形成在第二浇口腔中。 第一栅极层选择性地形成在第一栅极腔上的第一功函数材料层和栅极绝缘层之上。 第二势垒层形成在第一栅极腔中的第一势垒层上方，并且在第二栅极腔中的第二功函数材料层和栅极绝缘层之上。 在存在处理物质的情况下，在第一和第二栅极腔中的第二阻挡层上方形成导电材料，以限定第一和第二栅电极结构。

公开(公告)号：US09466491B2

公开(公告)日：2016-10-11

申请号：US14268579

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Hyun-Jin Cho ,  Ruilong Xie

IPC: H01L21/28 ,  H01L21/283 ,  H01L29/423 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L21/28 ,  H01L21/28247 ,  H01L21/283 ,  H01L21/76897 ,  H01L29/417 ,  H01L29/41775 ,  H01L29/423 ,  H01L29/42364 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲栅极结构，在牺牲栅极结构的相对侧面上形成侧壁隔离物，去除牺牲栅极结构并在其位置形成替代栅极结构 在形成替代栅极结构之后的某些点，执行蚀刻工艺以降低间隔物的高度，从而限定具有部分限定间隔物凹槽的上表面的凹进的间隔件，并且在上表面上形成间隔物蚀刻块帽 每个凹进的间隔结构和间隔凹槽内。

公开(公告)号：US20160293706A1

公开(公告)日：2016-10-06

申请号：US15186632

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: A FinFET device includes a substrate, a gate structure positioned above the substrate, and sidewall spacers positioned adjacent to the gate structure. An epi semiconductor material is positioned in source and drain regions of the FinFET device and laterally outside of the sidewall spacers. A fin extends laterally under the gate structure and the sidewall spacers in a gate length direction of the FinFET device, wherein the end surfaces of the fin abut and engage the epi semiconductor material. A stressed material is positioned in a channel cavity located below the fin, above the substrate, and laterally between the epi semiconductor material, the stressed material having a top surface that abuts and engages a bottom surface of the fin, a bottom surface that abuts and engages the substrate, and end surfaces that abut and engage the epi semiconductor material.

Abstract translation: FinFET器件包括衬底，位于衬底上方的栅极结构以及邻近栅极结构定位的侧壁间隔物。 外延半导体材料位于FinFET器件的源极和漏极区域中，并且横向在侧壁间隔物的外侧。 翅片在FinFET器件的栅极长度方向上在栅极结构和侧壁间隔物之下横向延伸，其中鳍片的端面抵靠并接合外延半导体材料。 应力材料定位在位于翅片下方的衬底上方的通道腔中，并且横向地位于外延半导体材料之间，受压材料具有邻接并接合翅片的底表面的顶表面，邻接的底表面和 接合基板以及邻接和接合外延半导体材料的端面。