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    MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
    441.
    发明申请
    MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD 审中-公开
    使用BUFFER（S）在母板上的存储器系统设计

    公开(公告)号：US20160364347A1

    公开(公告)日：2016-12-15

    申请号：US15071072

    申请日：2016-03-15

    Applicant: Rambus Inc.

    Inventor： Chi-Ming YEUNG ,  Yoshie NAKABAYASHI ,  Thomas GIOVANNINI ,  Henry STRACOVSKY

    IPC: G06F13/16 ,  G06F15/78 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/1673 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282

    Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

    Abstract translation: 一种母板拓扑，包括可操作以耦合到一个或多个通信信道以用于传达命令的处理器。 该拓扑包括将母线上的第一组两个或多个双列直插存储器模块（DIMM）和第一主数据缓冲器电耦合的第一通信信道。 该拓扑包括第二通信通道，电连接第二组两个或更多个DIMM和母板上的第二主数据缓冲器。 该拓扑包括电耦合第一主数据缓冲器，主第二数据缓冲器和处理器的第三通道。

    Method and system for synchronizing address and control signals in threaded memory modules
    443.
    发明授权
    Method and system for synchronizing address and control signals in threaded memory modules 有权
    方法和系统，用于在螺纹存储器模块中同步地址和控制信号

    公开(公告)号：US09507738B2

    公开(公告)日：2016-11-29

    申请号：US14284473

    申请日：2014-05-22

    Applicant: Rambus Inc.

    Inventor： Arun Vaidyanath ,  Craig E. Hampel

    IPC: G06F12/00 ,  G06F13/16 ,  G11C5/04 ,  G11C5/06 ,  G11C8/18 ,  G11C29/02 ,  G06F12/06 ,  G11C7/10

    CPC classification number: G06F13/16 ,  G06F12/06 ,  G06F13/1689 ,  G06F2212/251 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1072 ,  G11C8/18 ,  G11C29/023 ,  G11C29/025 ,  G11C29/027

    Abstract: A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time.

    Abstract translation: 存储器系统包括还包括一组存储器件的存储器模块。 该组存储器件包括存储器件的第一子集和存储器件的第二子集。 地址总线设置在存储器模块上，其中地址总线包括耦合到第一子集的第一段和耦合到第二子集的第二段。 地址信号依次遍历该组存储器件。 存储器系统还包括耦合到存储器模块的存储器控​​制器。 存储器控制器包括第一电路，用于输出控制第一子集的第一控制信号，使得第一控制信号和地址信号在基本上同时到达第一子集中的存储器件。 存储器控制器还包括第二电路，用于输出控制第二子集的第二控制信号，使得第二控制信号和地址信号在基本上同时到达第二子集中的存储器件。

    Virtualized cache memory
    444.
    发明授权
    Virtualized cache memory 有权
    虚拟缓存内存

    公开(公告)号：US09507731B1

    公开(公告)日：2016-11-29

    申请号：US14512254

    申请日：2014-10-10

    Applicant: Rambus Inc.

    Inventor： Hongzhong Zheng ,  Joseph James Tringali ,  Vidyabhushan Mohan

    IPC: G06F12/00 ,  G06F12/10 ,  G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/109 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/657

    Abstract: A memory address and a virtual cache identifier are received in association with a request to retrieve data from a cache data array. Context information is selected based on the virtual cache identifier, the context information indicating a first region of a plurality of regions within the cache data array. A cache line address that includes a first number of bits of the memory address in accordance with a size of the first region is generated and, if the cache data array is determined to contain, in a location indicated by the cache line address, a cache line corresponding to the memory address, the cache line is retrieved from the location indicated by the cache line address.

    Abstract translation: 与从缓存数据阵列检索数据的请求相关联地接收存储器地址和虚拟高速缓存标识符。 基于虚拟高速缓存标识符来选择上下文信息，上下文信息指示高速缓存数据阵列内的多个区域的第一区域。 生成包括根据第一区域的大小的存储器地址的第一位数的高速缓存行地址，并且如果高速缓存数据阵列被确定为包含在由高速缓存线地址指示的位置中的高速缓存 对应于存储器地址的行，从由高速缓存行地址指示的位置检索高速缓存行。

    MEMORY CONTROLLER WITH PHASE ADJUSTED CLOCK FOR PERFORMING MEMORY OPERATIONS
    445.
    发明申请
    MEMORY CONTROLLER WITH PHASE ADJUSTED CLOCK FOR PERFORMING MEMORY OPERATIONS 有权
    用于执行存储器操作的具有相位调节时钟的存储器控​​制器

    公开(公告)号：US20160343417A1

    公开(公告)日：2016-11-24

    申请号：US15160538

    申请日：2016-05-20

    Applicant: Rambus Inc.

    Inventor： Ian P. Shaeffer ,  Lei Luo

    IPC: G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C7/10 ,  G06F1/08

    CPC classification number: G11C7/22 ,  G06F1/08 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4243 ,  G11C7/1072

    Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

    Abstract translation: 在说明性实施例中，存储器电路包括用于读和写存储器操作的数据被传送的第一和第二数据路径，以及用于调整施加到其输入的时钟信号的相位的第一和第二混频器电路。 混频器电路交叉耦合，使得第一和第二混频器的输出都可用于第一和第二数据路径。 一个混频器用于提供第一相位调整的时钟信号供操作电路使用，另一个混频器用于提供第二相位调整的时钟信号，供随后的操作使用。

    Methods and systems for transmitting data by modulating transmitter filter coefficients
    447.
    发明授权
    Methods and systems for transmitting data by modulating transmitter filter coefficients 有权
    通过调制发射机滤波器系数传输数据的方法和系统

    公开(公告)号：US09491011B2

    公开(公告)日：2016-11-08

    申请号：US14448006

    申请日：2014-07-31

    Applicant: Rambus Inc.

    Inventor： Jaeha Kim ,  Haechang Lee ,  Jung-Hoon Chun ,  Jared Zerbe

    IPC: H04B1/10 ,  H04L25/03 ,  H04L5/04 ,  H04B1/12

    CPC classification number: H04L25/03343 ,  H04B1/126 ,  H04L5/04 ,  H04L2025/03356 ,  H04L2025/03477 ,  H04L2025/03802

    Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.

    Abstract translation: 信号系统通过单个链路在相同方向上支持集成电路之间的主要和辅助通信信道。 均衡发射机在通过通信信道发送主数据时，应用适当的滤波器系数来最小化符号间干扰的影响。 发射机利用辅助数据调制至少一个滤波器系数，以在发射信号中引起明显的ISI。 主接收机忽略明显的ISI以恢复主数据，而辅助接收机检测并解调明显的ISI以恢复辅助数据。 可以使用扩频技术对辅助数据进行编码，以减少辅助数据对主数据的影响。

    DYNAMIC TERMINATION SCHEME FOR MEMORY COMMUNICATION
    449.
    发明申请
    DYNAMIC TERMINATION SCHEME FOR MEMORY COMMUNICATION 审中-公开
    用于记忆通信的动态终止方案

    公开(公告)号：US20160291894A1

    公开(公告)日：2016-10-06

    申请号：US15051554

    申请日：2016-02-23

    Applicant: Rambus Inc.

    Inventor： Chi-Ming YEUNG ,  David SECKER ,  Ravindranath KOLLIPARA ,  Shajith Musaliar SIRAJUDEEN ,  Yoshie NAKABAYASHI

    IPC: G06F3/06 ,  G06F13/40

    CPC classification number: G06F13/4068

    Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.

    Abstract translation: 用于动态终止控制的系统和方法，以便在单个通道上使用增加数量的存储器模块。 在一些实施例中，六个或八个DIMM耦合到单个通道。 动态终止方案可以包括用于地址总线/命令总线的每个存储器模块上的输入总线终端（IBT）和用于数据总线的每个存储器模块的用于片上终止（ODT）的配置）的配置。

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