公开(公告)号：US20120063194A1

公开(公告)日：2012-03-15

申请号：US13224410

申请日：2011-09-02

申请人： In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

发明人： In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

摘要： Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

摘要翻译： 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

公开(公告)号：US20110286254A1

公开(公告)日：2011-11-24

申请号：US13108130

申请日：2011-05-16

申请人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

IPC分类号： G11C5/02

CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

公开(公告)号：US20110228582A1

公开(公告)日：2011-09-22

申请号：US13024566

申请日：2011-02-10

申请人： Chul-Woo PARK ,  Hong-Sun HWANG ,  In-Gyu BAEK ,  Dong-Hyun SOHN

发明人： Chul-Woo PARK ,  Hong-Sun HWANG ,  In-Gyu BAEK ,  Dong-Hyun SOHN

IPC分类号： G11C5/02 ,  G11C5/06 ,  H01L27/24 ,  H01L21/77

CPC分类号： H01L21/77 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/24

摘要： A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.

摘要翻译： 叠层半导体存储器件包括具有功能电路，多个存储单元阵列层以及至少一个连接层的半导体衬底。 存储单元阵列层堆叠在半导体衬底之上。 连接层堆叠在半导体衬底之上，独立于存储单元阵列层。 连接层将布置在存储单元阵列层上的存储单元选择线电连接到功能电路。

公开(公告)号：US07586804B2

公开(公告)日：2009-09-08

申请号：US11584565

申请日：2006-10-23

申请人： Hong-Sun Hwang

发明人： Hong-Sun Hwang

IPC分类号： G11C7/02

CPC分类号： G11C29/24 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2029/1204

摘要： A memory core and method thereof are provided. The example memory core may include an edge sub-array including a plurality of word lines, a plurality of bit lines, and a plurality of dummy bit lines, a sense amplifier circuit configured to amplify voltages of the plurality of dummy bit lines and a switching circuit configured to transfer at least one input data through the plurality of dummy bit lines, in response to at least one column select signal. The example method may include generating test input data in response to a test enable signal and a write signal, transferring the test input data to a plurality of dummy bit lines, in response to at least one column select signal and amplifying the test input data transferred to the plurality of dummy bit lines.

摘要翻译： 提供了一种记忆核心及其方法。 示例性存储器芯可以包括包括多个字线，多个位线和多个虚拟位线的边缘子阵列，被配置为放大多个虚拟位线的电压的读出放大器电路和切换 电路，被配置为响应于至少一个列选择信号，通过所述多个虚拟位线传送至少一个输入数据。 该示例性方法可以响应于至少一个列选择信号而产生测试输入数据，该测试输入数据响应于测试使能信号和写入信号，将测试输入数据传送到多个虚拟位线，并放大传输的测试输入数据 到多个虚拟位线。

公开(公告)号：US08693269B2

公开(公告)日：2014-04-08

申请号：US13569636

申请日：2012-08-08

申请人： Uk-song Kang ,  Chul-woo Park ,  Hak-soo Yu ,  Hong-sun Hwang

发明人： Uk-song Kang ,  Chul-woo Park ,  Hak-soo Yu ,  Hong-sun Hwang

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/4093

摘要： A method of performing write operations in a memory device including a plurality of bank is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

摘要翻译： 执行在包括多个存储体的存储器件中执行写入操作的方法。 每个银行包括至少包括第一子银行和第二子银行的两个或多个子行。 该方法包括：执行第一行周期以写入第一子行的第一字线，第一行周期包括多个第一子周期，用于执行特定动作的每个子周期; 以及执行第二行周期以写入所述第二子行的第一字线，所述第二行周期包括与所述多个第一子周期相同类型的多个第二子周期。 第一行周期与第二行周期重叠，第一子周期的第一类型子周期与第二子周期的第二类型子周期重叠，第一类型和第二类型是不同类型。

公开(公告)号：US08677216B2

公开(公告)日：2014-03-18

申请号：US13015850

申请日：2011-01-28

申请人： Chul-Woo Park ,  Hong-Sun Hwang ,  Kwan-Young Oh ,  Sang-Beom Kang

发明人： Chul-Woo Park ,  Hong-Sun Hwang ,  Kwan-Young Oh ,  Sang-Beom Kang

IPC分类号： G11C29/00

CPC分类号： G06F11/1044

摘要： A stacked semiconductor memory device includes an error correction code (ECC) controller that controls the number of bits in an ECC word and corrects errors in memory cell array layers using the ECC word.

摘要翻译： 叠层半导体存储器件包括纠错码（ECC）控制器，其控制ECC字中的位数，并使用ECC字来校正存储单元阵列层中的错误。

公开(公告)号：US20140068203A1

公开(公告)日：2014-03-06

申请号：US14013275

申请日：2013-08-29

申请人： JONG PIL SON ,  CHUL WOO PARK ,  HAK SOO YU ,  HONG SUN HWANG

发明人： JONG PIL SON ,  CHUL WOO PARK ,  HAK SOO YU ,  HONG SUN HWANG

IPC分类号： G06F3/06

CPC分类号： G06F3/061 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0676 ,  G06F3/068 ,  G06F13/1642 ,  G11C7/00 ,  G11C7/1048 ,  G11C11/4076 ,  Y02D10/14

摘要： A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

摘要翻译： 存储器系统包括存储器件和存储器控制器。 存储装置包括多个存储单元。 存储器控制器被配置为在活动命令和预充电命令之间在存储器设备上连续地执行多个写入命令。 在存储器系统中，当执行了具有多个写入命令的最后写入命令的第一次写入操作之后，然后执行预充电命令时，在预充电命令之后发出最后一个写入命令用于第二次写入操作。 第一写入操作和第二写入操作将相同的数据写入具有相同地址的多个存储单元的存储单元。

公开(公告)号：US08588017B2

公开(公告)日：2013-11-19

申请号：US13236972

申请日：2011-09-20

申请人： Chul-woo Park ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

发明人： Chul-woo Park ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

IPC分类号： G11C29/00

CPC分类号： G11C29/808 ,  G06F2213/0038 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C2211/4062

摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

摘要翻译： 存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作 命令。

公开(公告)号：US08477554B2

公开(公告)日：2013-07-02

申请号：US13152316

申请日：2011-06-03

申请人： Hak-soo Yu ,  In-gyu Baek ,  Hong-sun Hwang ,  Young-kug Moon

发明人： Hak-soo Yu ,  In-gyu Baek ,  Hong-sun Hwang ,  Young-kug Moon

IPC分类号： G11C5/14 ,  G11C5/02 ,  G11C5/06

CPC分类号： G11C5/063 ,  G11C5/025

摘要： A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers.

摘要翻译： 一种半导体存储器件，包括多个层，每个层包括存储单元阵列并彼此堆叠; 以及用于向层供电的至少一个电力平面。 电力平面包括施加电源电压的区域和施加接地电压的区域。 施加电源电压的区域位于与施加接地电压的区域相邻的位置处，并且在其间形成去耦电容器，以将功率噪声涌入到层中或在层中产生功率噪声。

公开(公告)号：US20130148429A1

公开(公告)日：2013-06-13

申请号：US13705143

申请日：2012-12-04

申请人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

发明人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC分类号： G11C7/06 ,  G11C11/16 ,  G11C16/26 ,  G11C13/00

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/28 ,  G11C27/02 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06

摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

摘要翻译： 提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。 第二开关被配置为接收第二CSL信号。 感测和锁存电路（SLC）耦合在第一和第二开关之间。 并且至少一个存储器单元耦合到第二开关。 第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。 存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。 还提供了使用这种存储器件执行读和写操作的方法。