公开(公告)号：US20240212743A1

公开(公告)日：2024-06-27

申请号：US18555714

申请日：2022-04-14

Applicant: Rambus, Inc.

Inventor： Christopher Haywood

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/42

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/42

Abstract: Technologies for concurrent interface operations of integrated circuit memory devices are described. An integrated circuit memory device includes an input port, a control port, and an output port. The input port receives interleaved input and a first timing reference. The interleaved input includes one or more commands or write data. The control port receives one or more control signals that specify that the interleaved input is the one or more commands or the write data. The output port transmits read data and a second timing reference. The commands or write data can be received concurrently with transmitting the read data.

公开(公告)号：US12014089B2

公开(公告)日：2024-06-18

申请号：US18121231

申请日：2023-03-14

Applicant: Rambus Inc.

Inventor： Frederick Ware

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0683 ,  G06F12/06 ,  G06F13/1689 ,  G06F13/4086 ,  G06F13/4256 ,  G06F13/1684

Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

公开(公告)号：US12007916B2

公开(公告)日：2024-06-11

申请号：US18295143

申请日：2023-04-03

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0646 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22 ,  G06F13/1678 ,  G06F2212/7206

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US20240177794A1

公开(公告)日：2024-05-30

申请号：US18367381

申请日：2023-09-12

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C29/52 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C29/52 ,  G11C11/4087 ,  G11C11/4093

Abstract: Technologies for dynamic random access memory (DRAM) devices with variable burst lengths are described. One DRAM device includes a first mode of operation having a first burst length and a first column address range and a second mode of operation having a second burst length and a second column address range. Only one of the first burst length and the second burst length is a power of two. A first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same. The DRAM device includes an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation.

公开(公告)号：US20240176497A1

公开(公告)日：2024-05-30

申请号：US18519359

申请日：2023-11-27

Applicant: Rambus Inc.

Inventor： Liji GOPALAKRISHNAN ,  Thomas VOGELSANG ,  John Eric LINSTADT

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40622 ,  G06F13/1636

Abstract: ABSTRACT OF DISCLOSURE A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.

公开(公告)号：US20240168873A1

公开(公告)日：2024-05-23

申请号：US18162824

申请日：2021-08-06

Applicant: Rambus Inc.

Inventor： Andrew M. Fuller ,  Barry William Daly ,  Thomas J. Giovannini ,  Lei Luo ,  Masum Hossain

IPC: G06F12/02 ,  G11C11/408

CPC classification number: G06F12/0223 ,  G11C11/4082

Abstract: Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing-reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.

公开(公告)号：US11990912B2

公开(公告)日：2024-05-21

申请号：US17883345

申请日：2022-08-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

IPC: H03K5/13 ,  G06F13/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02

CPC classification number: H03K5/13 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G06F13/00 ,  G06F13/4243 ,  G11C7/04

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

公开(公告)号：US20240146546A1

公开(公告)日：2024-05-02

申请号：US18278374

申请日：2022-02-25

Applicant: Rambus Inc.

Inventor： Scott C. BEST ,  Thomas VOGELSANG ,  Michael Alexander HAMBURG ,  Mark Evan MARSON ,  Helena HANDSCHUH ,  HAMPEL E. Craig ,  Kenneth Lee WRIGHT

IPC: H04L9/32 ,  G06F21/73

CPC classification number: H04L9/3268 ,  G06F21/73

Abstract: An asymmetric key cryptographic system is used to generate a cryptographic certificate for authenticating a memory module. This certificate is generated based on information, readable by the authenticator (e.g., host system), from at least one device on the memory module that is not read in order to obtain the certificate. For example, the certificate for authenticating a module may be stored in the nonvolatile memory of a serial presence detect device. The certificate itself, however, is based at least in part on information read from at least one other device on the memory module. Examples of this other device include a registering clock driver, DRAM device(s), and/or data buffer device(s). In an embodiment, the information read from a device (e.g., DRAM) may be based on one or more device fingerprint(s) derived from physical variations that occur naturally, and inevitably, during integrated circuit manufacturing.

公开(公告)号：US20240146304A1

公开(公告)日：2024-05-02

申请号：US18504032

申请日：2023-11-07

Applicant: Rambus Inc.

Inventor： Huy Nguyen

IPC: H03K19/00 ,  H04B1/04 ,  H04L25/02

CPC classification number: H03K19/0005 ,  H04B1/0458 ,  H04L25/0278 ,  H04L25/0298

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

公开(公告)号：US11967364B2

公开(公告)日：2024-04-23

申请号：US18203511

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G06F11/10 ,  G11C7/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.